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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date:        19. March 2015
* $Revision: 	V.1.4.5
*
* Project: 	    CMSIS DSP Library
* Title:	    arm_common_tables.h
*
* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*   - Redistributions of source code must retain the above copyright
*     notice, this list of conditions and the following disclaimer.
*   - Redistributions in binary form must reproduce the above copyright
*     notice, this list of conditions and the following disclaimer in
*     the documentation and/or other materials provided with the
*     distribution.
*   - Neither the name of ARM LIMITED nor the names of its contributors
*     may be used to endorse or promote products derived from this
*     software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */

#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H

#include "arm_math.h"

extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
//extern const q31_t realCoefAQ31[1024];
//extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];


/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)

extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];

/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];

/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];

#endif /*  ARM_COMMON_TABLES_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 16:20:30 +0000
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the following APIs: (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation (#) You can continuously monitor the SRAM device HAL state by calling the function HAL_SRAM_GetState() @endverbatim ****************************************************************************** * @attention * * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ */ /** @defgroup SRAM SRAM * @brief SRAM driver modules * @{ */ #ifdef HAL_SRAM_MODULE_ENABLED #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup SRAM_Exported_Functions SRAM Exported Functions * @{ */ /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### SRAM Initialization and de_initialization functions ##### ============================================================================== [..] This section provides functions allowing to initialize/de-initialize the SRAM memory @endverbatim * @{ */ /** * @brief Performs the SRAM device initialization sequence * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param Timing: Pointer to SRAM control timing structure * @param ExtTiming: Pointer to SRAM extended mode timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the SRAM handle parameter */ if(hsram == NULL) { return HAL_ERROR; } if(hsram->State == HAL_SRAM_STATE_RESET) { /* Allocate lock resource and initialize it */ hsram->Lock = HAL_UNLOCKED; /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); } /* Initialize SRAM control Interface */ FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); /* Initialize SRAM timing Interface */ FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); /* Initialize SRAM extended mode timing Interface */ FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); return HAL_OK; } /** * @brief Performs the SRAM device De-initialization sequence. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) { /* De-Initialize the low level hardware (MSP) */ HAL_SRAM_MspDeInit(hsram); /* Configure the SRAM registers with their reset values */ FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); hsram->State = HAL_SRAM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief SRAM MSP Init. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspInit could be implemented in the user file */ } /** * @brief SRAM MSP DeInit. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspDeInit could be implemented in the user file */ } /** * @brief DMA transfer complete callback. * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file */ } /** * @brief DMA transfer complete error callback. * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval None */ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions * @brief Input Output and memory control functions * @verbatim ============================================================================== ##### SRAM Input and Output functions ##### ============================================================================== [..] This section provides functions allowing to use and control the SRAM memory @endverbatim * @{ */ /** * @brief Reads 8-bit buffer from SRAM memory. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) { __IO uint8_t * pSramAddress = (uint8_t *)pAddress; /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ for(; BufferSize != 0; BufferSize--) { *pDstBuffer = *(__IO uint8_t *)pSramAddress; pDstBuffer++; pSramAddress++; } /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Writes 8-bit buffer to SRAM memory. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) { __IO uint8_t * pSramAddress = (uint8_t *)pAddress; /* Check the SRAM controller state */ if(hsram->State == HAL_SRAM_STATE_PROTECTED) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ for(; BufferSize != 0; BufferSize--) { *(__IO uint8_t *)pSramAddress = *pSrcBuffer; pSrcBuffer++; pSramAddress++; } /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Reads 16-bit buffer from SRAM memory. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) { __IO uint16_t * pSramAddress = (uint16_t *)pAddress; /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ for(; BufferSize != 0; BufferSize--) { *pDstBuffer = *(__IO uint16_t *)pSramAddress; pDstBuffer++; pSramAddress++; } /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Writes 16-bit buffer to SRAM memory. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) { __IO uint16_t * pSramAddress = (uint16_t *)pAddress; /* Check the SRAM controller state */ if(hsram->State == HAL_SRAM_STATE_PROTECTED) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ for(; BufferSize != 0; BufferSize--) { *(__IO uint16_t *)pSramAddress = *pSrcBuffer; pSrcBuffer++; pSramAddress++; } /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Reads 32-bit buffer from SRAM memory. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) { /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ for(; BufferSize != 0; BufferSize--) { *pDstBuffer = *(__IO uint32_t *)pAddress; pDstBuffer++; pAddress++; } /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Writes 32-bit buffer to SRAM memory. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) { /* Check the SRAM controller state */ if(hsram->State == HAL_SRAM_STATE_PROTECTED) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ for(; BufferSize != 0; BufferSize--) { *(__IO uint32_t *)pAddress = *pSrcBuffer; pSrcBuffer++; pAddress++; } /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Reads a Words data from the SRAM memory using DMA transfer. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to read start address * @param pDstBuffer: Pointer to destination buffer * @param BufferSize: Size of the buffer to read from memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) { /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Configure DMA user callbacks */ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; /* Enable the DMA Stream */ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Writes a Words data buffer to SRAM memory using DMA transfer. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress: Pointer to write start address * @param pSrcBuffer: Pointer to source buffer to write * @param BufferSize: Size of the buffer to write to memory * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) { /* Check the SRAM controller state */ if(hsram->State == HAL_SRAM_STATE_PROTECTED) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Configure DMA user callbacks */ hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; /* Enable the DMA Stream */ HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @} */ /** @defgroup SRAM_Exported_Functions_Group3 Control functions * @brief management functions * @verbatim ============================================================================== ##### SRAM Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the SRAM interface. @endverbatim * @{ */ /** * @brief Enables dynamically SRAM write operation. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) { /* Process Locked */ __HAL_LOCK(hsram); /* Enable write operation */ FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @brief Disables dynamically SRAM write operation. * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL status */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) { /* Process Locked */ __HAL_LOCK(hsram); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; /* Disable write operation */ FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_PROTECTED; /* Process unlocked */ __HAL_UNLOCK(hsram); return HAL_OK; } /** * @} */ /** @defgroup SRAM_Exported_Functions_Group4 State functions * @brief Peripheral State functions * @verbatim ============================================================================== ##### SRAM State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the SRAM controller and the data flow. @endverbatim * @{ */ /** * @brief Returns the SRAM controller state * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @retval HAL state */ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) { return hsram->State; } /** * @} */ /** * @} */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_SRAM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 16:20:29 +0000