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-rw-r--r--toolruns/quartus/terasic_de0/external_avalanche_entropy.qpf30
-rw-r--r--generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 06:59:22 +0000 div class='add'>+set_location_assignment PIN_F3 -to debug[5]
+set_location_assignment PIN_B1 -to debug[6]
+set_location_assignment PIN_L3 -to debug[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to debug[7]
+set_location_assignment PIN_D3 -to noise
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to noise
+set_global_assignment -name SDC_FILE //psf/Home/Sandbox/proj/cores/external_avalanche_entropy/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc b/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc
new file mode 100644
index 0000000..ed97c9c
--- /dev/null
+++ b/toolruns/quartus/terasic_de0/external_avalanche_entropy.sdc
@@ -0,0 +1,40 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.
+#
+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
+#
+#************************************************************
+
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "clk" -period 20.000ns [get_ports {clk}] -waveform {0 10.000}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 06:59:22 +0000