CC=arm-none-eabi-gcc
AR=arm-none-eabi-ar

###########################################

vpath %.c targets/cmsis/TARGET_STM/TARGET_STM32F4 targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_DEV_BRIDGE

SRCS =	stm32f4xx_hal.c \
	stm32f4xx_hal_adc.c \
	stm32f4xx_hal_adc_ex.c \
	stm32f4xx_hal_can.c \
	stm32f4xx_hal_cec.c \
	stm32f4xx_hal_cortex.c \
	stm32f4xx_hal_crc.c \
	stm32f4xx_hal_cryp.c \
	stm32f4xx_hal_cryp_ex.c \
	stm32f4xx_hal_dac.c \
	stm32f4xx_hal_dac_ex.c \
	stm32f4xx_hal_dcmi.c \
	stm32f4xx_hal_dcmi_ex.c \
	stm32f4xx_hal_dma2d.c \
	stm32f4xx_hal_dma.c \
	stm32f4xx_hal_dma_ex.c \
	stm32f4xx_hal_dsi.c \
	stm32f4xx_hal_eth.c \
	stm32f4xx_hal_flash.c \
	stm32f4xx_hal_flash_ex.c \
	stm32f4xx_hal_flash_ramfunc.c \
	stm32f4xx_hal_fmpi2c.c \
	stm32f4xx_hal_fmpi2c_ex.c \
	stm32f4xx_hal_gpio.c \
	stm32f4xx_hal_hash.c \
	stm32f4xx_hal_hash_ex.c \
	stm32f4xx_hal_hcd.c \
	stm32f4xx_hal_i2c.c \
	stm32f4xx_hal_i2c_ex.c \
	stm32f4xx_hal_i2s.c \
	stm32f4xx_hal_i2s_ex.c \
	stm32f4xx_hal_irda.c \
	stm32f4xx_hal_iwdg.c \
	stm32f4xx_hal_lptim.c \
	stm32f4xx_hal_ltdc.c \
	stm32f4xx_hal_ltdc_ex.c \
	stm32f4xx_hal_msp_template.c \
	stm32f4xx_hal_nand.c \
	stm32f4xx_hal_nor.c \
	stm32f4xx_hal_pccard.c \
	stm32f4xx_hal_pcd.c \
	stm32f4xx_hal_pcd_ex.c \
	stm32f4xx_hal_pwr.c \
	stm32f4xx_hal_pwr_ex.c \
	stm32f4xx_hal_qspi.c \
	stm32f4xx_hal_rcc.c \
	stm32f4xx_hal_rcc_ex.c \
	stm32f4xx_hal_rng.c \
	stm32f4xx_hal_rtc.c \
	stm32f4xx_hal_rtc_ex.c \
	stm32f4xx_hal_sai.c \
	stm32f4xx_hal_sai_ex.c \
	stm32f4xx_hal_sd.c \
	stm32f4xx_hal_sdram.c \
	stm32f4xx_hal_smartcard.c \
	stm32f4xx_hal_spdifrx.c \
	stm32f4xx_hal_spi.c \
	stm32f4xx_hal_sram.c \
	stm32f4xx_hal_tim.c \
	stm32f4xx_hal_tim_ex.c \
	stm32f4xx_hal_uart.c \
	stm32f4xx_hal_usart.c \
	stm32f4xx_hal_wwdg.c \
	stm32f4xx_ll_fmc.c \
	stm32f4xx_ll_fsmc.c \
	stm32f4xx_ll_sdmmc.c \
	stm32f4xx_ll_usb.c \
	cmsis_nvic.c \
	hal_tick.c

OBJS = $(SRCS:.c=.o)

all: libstmf4.a

libstmf4.a: $(OBJS)
	$(AR) -r $@ $(OBJS)

clean:
	rm -f $(OBJS) libstmf4.a
</form>
</td></tr></table>
<div class='path'>path: <a href='/wiki/blame/?id=86202308b68db7a6cf299c5fe3cdee4dc1850330'>root</a>/<a href='/wiki/blame/wiki?id=86202308b68db7a6cf299c5fe3cdee4dc1850330'>wiki</a>/<a href='/wiki/blame/wiki/RoughV1.trac?id=86202308b68db7a6cf299c5fe3cdee4dc1850330'>RoughV1.trac</a></div><div class='content'>blob: 57dfda9118c10d62f593eb4b77b3472f21af8fa9 (<a href='/wiki/plain/wiki/RoughV1.trac?id=86202308b68db7a6cf299c5fe3cdee4dc1850330'>plain</a>) (<a href='/wiki/tree/wiki/RoughV1.trac?id=86202308b68db7a6cf299c5fe3cdee4dc1850330'>tree</a>)
<table class='blame blob'>
<tr>
<td class='hashes'><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2021-02-14 01:55:38 +0000
committer  Rob Austein &lt;sra@hactrn.net&gt;  2021-02-14 01:55:38 +0000

Hack images, store outputs in git again for now' href='/wiki/commit/tracwiki/RoughV1.trac?id=b58c60bcc4a6f3d3ccf4194ef862a808fdc3313b'>b58c60b</a></span>
























</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2021-02-14 17:47:46 +0000
committer  Rob Austein &lt;sra@hactrn.net&gt;  2021-02-14 17:47:46 +0000

Add image links' href='/wiki/commit/wiki/RoughV1.trac?id=92a5a007277005744740dabd36182410b87b6441'>92a5a00</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2021-02-14 01:55:38 +0000
committer  Rob Austein &lt;sra@hactrn.net&gt;  2021-02-14 01:55:38 +0000

Hack images, store outputs in git again for now' href='/wiki/commit/tracwiki/RoughV1.trac?id=b58c60bcc4a6f3d3ccf4194ef862a808fdc3313b'>b58c60b</a></span>





















































































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                                                                                                                                          </pre></div></div><pre><code><style>pre { line-height: 125%; }
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span>= Rough Cut at v0.01 Proof of Concept Feature Set =

[[PageOutline]]

This is a proposed version 0.01 product as a proof of concept.  The
intent is not to have a very useful product, but rather to gain
confidence in our architecture, tools, and team.  The result is intended
to be the basis for further development into a more useful second stage,
in the sense of 
[https://en.wikipedia.org/wiki/Agile_software_development agile development].
It very intentionally is not a
[https://en.wikipedia.org/wiki/Waterfall_model waterfall design],

The interface between the Green and Yellow layers is seen as an important design
inflection.

Some code will be in C in the Green (auxiliary core) because we can get it open 
source out of the can.  for v.2 (or whatever) we would move it down to the FPGA in
Verilog.

== FPGA Overview ==
[[Image(HW_sketch_v0001.png)]]
\\
\\
== Sketch of TRNG Chain ==
[[Image(HW_RNG.png)]]
\\
\\

== Off-FPGA ==
* Persistent Storage
 * For Keys and Time
 * Or the battery for tamper wipe is big enough to hold the FPGA up
 * Or the Green processor has enough non-volatile store
* Entropy Source
* Realtime Clock
* Tamper Mechanism

== Layers ==

{{{
#!html
&lt;h1 style=&quot;text-align: left; color: blue&quot;&gt;
  Blue / FPGA
&lt;/h1&gt;
}}}

* TRNG
* !BigNumber, Modular, &amp; Exponentiation (expose to green for RSA)
* SHA-256
* AES-128
* EC for ECDH. Curve3617 would be nice, but whatever we can get open source to start
* OpenRISC Core or ARM to support Green (maybe !FreeScale from Bunnie)

{{{
#!html
&lt;h1 style=&quot;text-align: left; color: green&quot;&gt;
  Green / On-Chip Core
&lt;/h1&gt;
}}}

* RSA 2048 &amp; 4096 (move to blue later) [ 1024 for Tor? ]
* MACs: HMAC, 1305, uMAC
* DH (move to blue later)
* Device Activation, Move Authorization, Wiping

{{{
#!html
&lt;h1 style=&quot;text-align: left; color: yellow&quot;&gt;
  Yellow / Off-Chip Support
&lt;/h1&gt;
}}}

* Interface to Red
 * PKCS!#8
 * PKCS!#11
 * PGP Support
* X.509 and PGP
* PKCS!#11 for POLA resistance
* No PKCS!#10 because it will take a year
* Backup may be just dump/restore of the whole FPGA/!CoreState

{{{
#!html
&lt;h1 style=&quot;text-align: left; color: red&quot;&gt;
  Red / Applications
&lt;/h1&gt;
}}}

* X.509 CA
* DNSSEC
* PGP (asymmetric key sign/verify + symmetric message encryption/decryption)
* Tor consensus(?)

== Issues in v0.01 ==

* License of tool chain to build
* License for borrowed components (open cores, open fpga)
* License for result
 * What we build ourselves - BSD
 * What components we ship - life is compromise
* Toolchains, Verilog, C, ...
* FPGAs and ASICs use a Verilog-based toolchain.  There are no mature open
  Verilog compilers so the [http://www.dwheeler.com/trusting-trust/ DDC approach]
  will not work.  Net-list optimization is also an issue.  We&#39;re looking into this, 
  but it&#39;s going to be really hard.  Research for v2.
* Protoyping platform
 * [http://www.bunniestudios.com/blog/?p=3265 Bunnie&#39;s Novena laptop]
 * Altera Evaluation Board
* RTC, external connectivity to et some sort of assured time
* Repository - too many git junkies.  Keep main repo on our server for the security boundary.  Can mirror on !GitHub to be socially cool.
* Emacs or vi (no Rob, not TECO) :)
</pre></div>