From 523d1f66453e9b92835ecc661085e4575426e661 Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Wed, 18 May 2016 21:14:52 +0200 Subject: Add FPGA bitstream upload command to cli-test. This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164 --- stm-fpgacfg.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'stm-fpgacfg.h') diff --git a/stm-fpgacfg.h b/stm-fpgacfg.h index bed3b38..fa5c4ef 100644 --- a/stm-fpgacfg.h +++ b/stm-fpgacfg.h @@ -75,6 +75,9 @@ extern int n25q128_read_page(uint32_t page_offset, uint8_t *page_buffer); extern int n25q128_write_page(uint32_t page_offset, uint8_t *page_buffer); extern int n25q128_erase_sector(uint32_t sector_offset); +extern void fpgacfg_give_access_to_stm32(void); +extern void fpgacfg_give_access_to_fpga(void); + extern SPI_HandleTypeDef hspi_fpgacfg; #endif /* __STM32_FPGACFG_H */ -- cgit v1.2.3