From 523d1f66453e9b92835ecc661085e4575426e661 Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Wed, 18 May 2016 21:14:52 +0200 Subject: Add FPGA bitstream upload command to cli-test. This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164 --- .../TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libraries') diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c index c6a8a67..d0f814e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c @@ -216,7 +216,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) GPIO_InitTypeDef GPIO_InitStruct; if (hspi->Instance == SPI2) { /* Peripheral clock enable */ - __HAL_RCC_SPI2_CLK_ENABLE(); + __SPI2_CLK_ENABLE(); /* SPI2 is the FPGA config memory. * -- cgit v1.2.3