From 3b044e50d3295c04863bdb0587a6eef157e654b8 Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Wed, 18 May 2016 14:10:09 +0200 Subject: FPGA config memory access code from Pavel. --- .../TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_conf.h | 2 +- .../TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c | 36 +++++++++++++++++++++- 2 files changed, 36 insertions(+), 2 deletions(-) (limited to 'libraries') diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_conf.h index 31c0e31..3844481 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_conf.h @@ -78,7 +78,7 @@ //#define HAL_RTC_MODULE_ENABLED //#define HAL_SAI_MODULE_ENABLED //#define HAL_SD_MODULE_ENABLED -//#define HAL_SPI_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED //#define HAL_USART_MODULE_ENABLED diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c index a430c5e..c6a8a67 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c @@ -182,6 +182,8 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) GPIO_InitTypeDef GPIO_InitStruct; if (hi2c->Instance == I2C2) { /* + * External RTC chip. + * * I2C2 GPIO Configuration * PH5 ------> I2C2_SDA * PH4 ------> I2C2_SCL @@ -203,11 +205,43 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) { - if(hi2c->Instance == I2C2) { + if (hi2c->Instance == I2C2) { __I2C2_CLK_DISABLE(); HAL_GPIO_DeInit(GPIOH, GPIO_PIN_4 | GPIO_PIN_5); } } +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct; + if (hspi->Instance == SPI2) { + /* Peripheral clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + /* SPI2 is the FPGA config memory. + * + * SPI2 GPIO Configuration + * PB13 ------> SPI2_SCK + * PB14 ------> SPI2_MISO + * PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + } +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if (hspi->Instance == SPI2) { + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); + } +} /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3