| Age | Commit message (Collapse) | Author |
|---|
|
|
|
Makes more sense to keep them together, at least in the cli-test.
|
|
|
|
|
|
|
|
DMA is more efficient and less prone to miss characters than interrupts.
An open question is if circular mode is really the best. If someone
copy-pastes more than the RX buffer size of configuration into the CLI,
we risk the DMA controller catching up with the reader and overwriting
data not yet read.
Since we don't have flow control back to the users terminal, we will
always fail if too much data is entered before we can process it. The
question is if failing to stuff new data at the end of a buffer might be
better than data being overwritten - thus messing up the commands in
unpredictable ways.
|
|
|
|
|
|
|
|
|
|
This bootloader is now the application at 0x08000000 (FLASH start),
which the STM32 will execute upon reset.
The other applications are now loaded at 0x08030000 (128 KB into the
flash) and will never get started unless the bootloader has been
programmed into flash too.
|
|
The applications to be uploaded using 'dfu upload' have to have another
FLASH defined in their linker script.
Have to recompile some firmware tomorrow and test if this actually
works.
|
|
Committing my work in progress in case someone else wants to help.
|
|
|
|
Integrated into the cli-test program as such:
cryptech> test sdram
Initializing SDRAM
Starting SDRAM test (n = 0)
Run sequential write-then-read test for the first chip
Run random write-then-read test for the first chip
Run sequential write-then-read test for the second chip
Run random write-then-read test for the second chip
Run interleaved write-then-read test for both chips at once
SDRAM test (n = 0) completed
SDRAM test completed successfully
cryptech>
|
|
|
|
|
|
Hopefully, having this excitement now makes adding commands a little bit
less exciting from here on.
|
|
Also add code to erase FPGA config memory and check status of FPGA_DONE.
|
|
Move the N25Q128 code to it's own file in order to be able to reuse it
for the keystore memory code.
|
|
This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:
filetransfer --fpga /path/to/bitstream
The bitstream is identified by 'file' e.g. like this:
alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164
|
|
|
|
|
|
|
|
|
|
|
|
|
