1 files changed, 0 insertions, 80 deletions
diff --git a/stm-fmc.c b/stm-fmc.c
index 1302564..c5086b4 100644
--- a/stm-fmc.c
+++ b/stm-fmc.c
@@ -164,83 +164,3 @@ void fmc_init(void)
     // initialize fmc
     HAL_SRAM_Init(&_fmc_fpga_inst, &fmc_timing, NULL);
 }
-
-
-static HAL_StatusTypeDef _fmc_nwait_idle(void)
-{
-    int cnt;
-
-    // poll NWAIT (number of iterations is limited)
-    for (cnt=0; cnt<FMC_FPGA_NWAIT_MAX_POLL_TICKS; cnt++)
-    {
-        // read pin state
-        if (HAL_GPIO_ReadPin(FMC_GPIO_PORT_NWAIT, FMC_GPIO_PIN_NWAIT) == FMC_NWAIT_IDLE)
-            return HAL_OK;
-    }
-
-    return HAL_ERROR;
-}
-
-HAL_StatusTypeDef fmc_write_32(uint32_t addr, uint32_t *data)
-{
-    // calculate target fpga address
-    uint32_t ptr = FMC_FPGA_BASE_ADDR + (addr & FMC_FPGA_ADDR_MASK);
-
-    __disable_irq();
-
-    HAL_StatusTypeDef status =
-        // write data to fpga
-        HAL_SRAM_Write_32b(&_fmc_fpga_inst, (uint32_t *)ptr, data, 1);
-    if (status == HAL_OK)
-        // wait for transaction to complete
-        status = _fmc_nwait_idle();
-
-    __enable_irq();
-
-    return status;
-}
-
-static inline HAL_StatusTypeDef _fmc_read_32(uint32_t *ptr, uint32_t *data)
-{
-    HAL_StatusTypeDef status =
-        // read data from fpga
-        HAL_SRAM_Read_32b(&_fmc_fpga_inst, (uint32_t *)ptr, data, 1);
-    if (status == HAL_OK)
-        // wait for transaction to complete
-        status = _fmc_nwait_idle();
-
-    return status;
-}
-
-HAL_StatusTypeDef fmc_read_32(uint32_t addr, uint32_t *data)
-{
-    // calculate target fpga address
-    uint32_t ptr = FMC_FPGA_BASE_ADDR + (addr & FMC_FPGA_ADDR_MASK);
-
-    /* Pavel says:
-     * The short story is like, on one hand STM32 has a dedicated FMC_NWAIT
-     * pin, that can be used in variable-latency data transfer mode. On the
-     * other hand STM32 also has a very nasty hardware bug associated with
-     * FMC_WAIT, that causes processor to freeze under certain conditions.
-     * Because of this FMC_NWAIT cannot be used and FPGA can't properly signal
-     * to STM32, when data transfer is done. Because of that we have to read
-     * two times.
-     */
-
-    /* Add some level of reentrancy protection. When running under a
-     * preemptive multitasker, with two threads banging on the fpga, we appear
-     * to sometimes read the wrong value. I think this is because the second
-     * read counts on the first read to put the correct value on the address
-     * bus.
-     */
-    __disable_irq();
-
-    HAL_StatusTypeDef status =
-        _fmc_read_32((uint32_t *)ptr, data);
-    if (status == HAL_OK)
-        status = _fmc_read_32((uint32_t *)ptr, data);
-
-    __enable_irq();
-
-    return status;
-}