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-rw-r--r--projects/cli-test/cli-test.c365
1 files changed, 8 insertions, 357 deletions
diff --git a/projects/cli-test/cli-test.c b/projects/cli-test/cli-test.c
index 84c268b..ed6aac3 100644
--- a/projects/cli-test/cli-test.c
+++ b/projects/cli-test/cli-test.c
@@ -31,319 +31,22 @@
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "stm32f4xx_hal.h"
#include "stm-init.h"
#include "stm-led.h"
-#include "stm-uart.h"
-#include "stm-fpgacfg.h"
-#include "stm-keystore.h"
-#include "stm-sdram.h"
+
#include "mgmt-cli.h"
#include "mgmt-dfu.h"
-#include "test_sdram.h"
+#include "mgmt-fpga.h"
+#include "mgmt-misc.h"
+#include "mgmt-show.h"
+#include "mgmt-test.h"
#include <string.h>
-#include <stdlib.h>
-
-
-extern uint32_t update_crc(uint32_t crc, uint8_t *buf, int len);
-
-
-int cmd_show_cpuspeed(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- volatile uint32_t hclk;
-
- hclk = HAL_RCC_GetHCLKFreq();
- cli_print(cli, "HSE_VALUE: %li", HSE_VALUE);
- cli_print(cli, "HCLK: %li (%i MHz)", hclk, (int) hclk / 1000 / 1000);
- cli_print(cli, "SystemCoreClock: %li (%i MHz)", SystemCoreClock, (int) SystemCoreClock / 1000 / 1000);
- return CLI_OK;
-}
-
-int cmd_filetransfer(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- uint32_t filesize = 0, crc = 0, my_crc = 0, n = 256, counter = 0;
- uint8_t buf[256];
-
- cli_print(cli, "OK, write file size (4 bytes), data in %li byte chunks, CRC-32 (4 bytes)", n);
-
- uart_receive_bytes(STM_UART_MGMT, (void *) &filesize, 4, 1000);
- cli_print(cli, "File size %li", filesize);
-
- while (filesize) {
- if (filesize < n) {
- n = filesize;
- }
-
- if (uart_receive_bytes(STM_UART_MGMT, (void *) &buf, n, 1000) != HAL_OK) {
- cli_print(cli, "Receive timed out");
- return CLI_ERROR;
- }
- filesize -= n;
- my_crc = update_crc(my_crc, buf, n);
- counter++;
- uart_send_bytes(STM_UART_MGMT, (void *) &counter, 4);
- }
-
- cli_print(cli, "Send CRC-32");
- uart_receive_bytes(STM_UART_MGMT, (void *) &crc, 4, 1000);
- cli_print(cli, "CRC-32 %li", crc);
- if (crc == my_crc) {
- cli_print(cli, "CRC checksum MATCHED");
- } else {
- cli_print(cli, "CRC checksum did NOT match");
- }
-
- return CLI_OK;
-}
-
-int cmd_show_fpga_status(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- cli_print(cli, "FPGA has %sloaded a bitstream", fpgacfg_check_done() ? "":"NOT ");
- return CLI_OK;
-}
-
-int cmd_show_keystore_status(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- cli_print(cli, "Keystore memory is %sonline", (keystore_check_id() != 1) ? "NOT ":"");
- return CLI_OK;
-}
-
-int cmd_show_keystore_data(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- uint8_t buf[KEYSTORE_PAGE_SIZE];
- uint32_t i;
-
- if (keystore_check_id() != 1) {
- cli_print(cli, "ERROR: The keystore memory is not accessible.");
- }
-
- memset(buf, 0, sizeof(buf));
- if ((i = keystore_read_data(0, buf, sizeof(buf))) != 1) {
- cli_print(cli, "Failed reading first page from keystore memory: %li", i);
- return CLI_ERROR;
- }
-
- cli_print(cli, "First page from keystore memory:\r\n");
- uart_send_hexdump(STM_UART_MGMT, buf, 0, sizeof(buf) - 1);
- uart_send_string2(STM_UART_MGMT, (char *) "\r\n\r\n");
-
- for (i = 0; i < 8; i++) {
- if (buf[i] == 0xff) break; /* never written */
- if (buf[i] != 0x55) break; /* something other than a tombstone */
- }
- /* As a demo, tombstone byte after byte of the first 8 bytes in the keystore memory
- * (as long as they do not appear to contain real data).
- * If all of them are tombstones, erase the first sector to start over.
- */
- if (i < 8) {
- if (buf[i] == 0xff) {
- cli_print(cli, "Tombstoning byte %li", i);
- buf[i] = 0x55;
- if ((i = keystore_write_data(0, buf, sizeof(buf))) != 1) {
- cli_print(cli, "Failed writing data at offset 0: %li", i);
- return CLI_ERROR;
- }
- }
- } else {
- cli_print(cli, "Erasing first sector since all the first 8 bytes are tombstones");
- if ((i = keystore_erase_sectors(1)) != 1) {
- cli_print(cli, "Failed erasing the first sector: %li", i);
- return CLI_ERROR;
- }
- cli_print(cli, "Erase result: %li", i);
- }
-
- return CLI_OK;
-}
-
-/* The chunk size have to be a multiple of the SPI flash page size (256 bytes),
- and it has to match the chunk size in the program sending the bitstream over the UART.
-*/
-#define BITSTREAM_UPLOAD_CHUNK_SIZE 4096
-
-int cmd_fpga_bitstream_upload(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- uint32_t filesize = 0, crc = 0, my_crc = 0, counter = 0, i;
- uint32_t offset = 0, n = BITSTREAM_UPLOAD_CHUNK_SIZE;
- uint8_t buf[BITSTREAM_UPLOAD_CHUNK_SIZE];
-
- fpgacfg_access_control(ALLOW_ARM);
-
- cli_print(cli, "Checking if FPGA config memory is accessible");
- if (fpgacfg_check_id() != 1) {
- cli_print(cli, "ERROR: FPGA config memory not accessible. Check that jumpers JP7 and JP8 are installed.");
- return CLI_ERROR;
- }
-
- cli_print(cli, "OK, write FPGA bitstream file size (4 bytes), data in 4096 byte chunks, CRC-32 (4 bytes)");
-
- /* Read file size (4 bytes) */
- uart_receive_bytes(STM_UART_MGMT, (void *) &filesize, 4, 1000);
- cli_print(cli, "File size %li", filesize);
-
- while (filesize) {
- /* By initializing buf to the same value that erased flash has (0xff), we don't
- * have to try and be smart when writing the last page of data to the memory.
- */
- memset(buf, 0xff, sizeof(buf));
-
- if (filesize < n) {
- n = filesize;
- }
-
- if (uart_receive_bytes(STM_UART_MGMT, (void *) &buf, n, 1000) != HAL_OK) {
- cli_print(cli, "Receive timed out");
- return CLI_ERROR;
- }
- filesize -= n;
-
- /* After reception of 4 KB but before ACKing we have "all" the time in the world to
- * calculate CRC and write it to flash.
- */
- my_crc = update_crc(my_crc, buf, n);
- if ((i = fpgacfg_write_data(offset, buf, BITSTREAM_UPLOAD_CHUNK_SIZE)) != 1) {
- cli_print(cli, "Failed writing data at offset %li (counter = %li): %li", offset, counter, i);
- return CLI_ERROR;
- }
- offset += BITSTREAM_UPLOAD_CHUNK_SIZE;
+/* MGMT UART interrupt receive buffer (data will be put in a larger ring buffer) */
+volatile uint8_t uart_rx;
- /* ACK this chunk by sending the current chunk counter (4 bytes) */
- counter++;
- uart_send_bytes(STM_UART_MGMT, (void *) &counter, 4);
- }
-
- /* The sending side will now send it's calculated CRC-32 */
- cli_print(cli, "Send CRC-32");
- uart_receive_bytes(STM_UART_MGMT, (void *) &crc, 4, 1000);
- cli_print(cli, "CRC-32 %li", crc);
- if (crc == my_crc) {
- cli_print(cli, "CRC checksum MATCHED");
- } else {
- cli_print(cli, "CRC checksum did NOT match");
- }
-
- fpgacfg_access_control(ALLOW_FPGA);
-
- return CLI_OK;
-}
-
-int cmd_fpga_bitstream_erase(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- fpgacfg_access_control(ALLOW_ARM);
-
- cli_print(cli, "Checking if FPGA config memory is accessible");
- if (fpgacfg_check_id() != 1) {
- cli_print(cli, "ERROR: FPGA config memory not accessible. Check that jumpers JP7 and JP8 are installed.");
- return CLI_ERROR;
- }
-
- /* Erasing the whole config memory takes a while, we just need to erase the first sector.
- * The bitstream has an EOF marker, so even if the next bitstream uploaded is shorter than
- * the current one there should be no problem.
- *
- * This command could be made to accept an argument indicating the whole memory should be erased.
- */
- if (! fpgacfg_erase_sectors(1)) {
- cli_print(cli, "Erasing first sector in FPGA config memory failed");
- return CLI_ERROR;
- }
-
- cli_print(cli, "Erased FPGA config memory");
- fpgacfg_access_control(ALLOW_FPGA);
-
- return CLI_OK;
-}
-
-int cmd_fpga_reset(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- fpgacfg_access_control(ALLOW_FPGA);
- fpgacfg_reset_fpga(RESET_FULL);
- cli_print(cli, "FPGA has been reset");
-
- return CLI_OK;
-}
-
-int cmd_fpga_reset_registers(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- fpgacfg_access_control(ALLOW_FPGA);
- fpgacfg_reset_fpga(RESET_REGISTERS);
- cli_print(cli, "FPGA registers have been reset");
-
- return CLI_OK;
-}
-
-int cmd_reboot(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- cli_print(cli, "\n\n\nRebooting\n\n\n");
- HAL_NVIC_SystemReset();
- while (1) {};
-}
-
-int cmd_test_sdram(struct cli_def *cli, const char *command, char *argv[], int argc)
-{
- // run external memory initialization sequence
- HAL_StatusTypeDef status;
- int ok, num_cycles = 1, i, test_completed;
-
- if (argc == 1) {
- num_cycles = strtol(argv[0], NULL, 0);
- if (num_cycles > 100) num_cycles = 100;
- if (num_cycles < 1) num_cycles = 1;
- }
-
- cli_print(cli, "Initializing SDRAM");
- status = sdram_init();
- if (status != HAL_OK) {
- cli_print(cli, "Failed initializing SDRAM: %i", (int) status);
- return CLI_OK;
- }
-
- for (i = 1; i <= num_cycles; i++) {
- cli_print(cli, "Starting SDRAM test (%i/%i)", i, num_cycles);
- test_completed = 0;
- // set LFSRs to some initial value, LFSRs will produce
- // pseudo-random 32-bit patterns to test our memories
- lfsr1 = 0xCCAA5533;
- lfsr2 = 0xCCAA5533;
-
- cli_print(cli, "Run sequential write-then-read test for the first chip");
- ok = test_sdram_sequential(SDRAM_BASEADDR_CHIP1);
- if (!ok) break;
-
- cli_print(cli, "Run random write-then-read test for the first chip");
- ok = test_sdram_random(SDRAM_BASEADDR_CHIP1);
- if (!ok) break;
-
- cli_print(cli, "Run sequential write-then-read test for the second chip");
- ok = test_sdram_sequential(SDRAM_BASEADDR_CHIP2);
- if (!ok) break;
-
- cli_print(cli, "Run random write-then-read test for the second chip");
- ok = test_sdram_random(SDRAM_BASEADDR_CHIP2);
- if (!ok) break;
-
- // turn blue led on (testing two chips at the same time)
- led_on(LED_BLUE);
-
- cli_print(cli, "Run interleaved write-then-read test for both chips at once");
- ok = test_sdrams_interleaved(SDRAM_BASEADDR_CHIP1, SDRAM_BASEADDR_CHIP2);
-
- led_off(LED_BLUE);
- test_completed = 1;
- cli_print(cli, "SDRAM test (%i/%i) completed\r\n", i, num_cycles);
- }
-
- if (! test_completed) {
- cli_print(cli, "SDRAM test failed (%i/%i)", i, num_cycles);
- } else {
- cli_print(cli, "SDRAM test completed successfully");
- }
-
- return CLI_OK;
-}
int check_auth(const char *username, const char *password)
{
@@ -354,57 +57,6 @@ int check_auth(const char *username, const char *password)
return CLI_OK;
}
-void configure_cli_show(struct cli_def *cli)
-{
- /* show */
- cli_command_root(show);
-
- /* show cpuspeed */
- cli_command_node(show, cpuspeed, "Show the speed at which the CPU currently operates");
-
- cli_command_branch(show, fpga);
- /* show fpga status*/
- cli_command_node(show_fpga, status, "Show status about the FPGA");
-
- cli_command_branch(show, keystore);
- /* show keystore status*/
- cli_command_node(show_keystore, status, "Show status of the keystore memory");
- cli_command_node(show_keystore, data, "Show the first page of the keystore memory");
-}
-
-void configure_cli_fpga(struct cli_def *cli)
-{
- /* fpga */
- cli_command_root(fpga);
- /* fpga reset */
- cli_command_node(fpga, reset, "Reset FPGA (config reset)");
- /* fpga reset registers */
- cli_command_node(fpga_reset, registers, "Reset FPGA registers (soft reset)");
-
- cli_command_branch(fpga, bitstream);
- /* fpga bitstream upload */
- cli_command_node(fpga_bitstream, upload, "Upload new FPGA bitstream");
- /* fpga bitstream erase */
- cli_command_node(fpga_bitstream, erase, "Erase FPGA config memory");
-}
-
-void configure_cli_test(struct cli_def *cli)
-{
- /* test */
- cli_command_root(test);
-
- /* test sdram */
- cli_command_node(test, sdram, "Run SDRAM tests");
-}
-
-static void configure_cli_misc(struct cli_def *cli)
-{
- /* filetransfer */
- cli_command_root_node(filetransfer, "Test file transfering");
- /* reboot */
- cli_command_root_node(reboot, "Reboot the STM32");
-}
-
typedef void (*pFunction)(void);
/* This is it's own function to make it more convenient to set a breakpoint at it in gdb */
@@ -419,7 +71,6 @@ void do_early_dfu_jump(void)
while (1);
}
-
int
main()
{
@@ -451,7 +102,7 @@ main()
/* embedded_cli_loop returns when the user enters 'quit' or 'exit' */
- cli_print(&cli, "Rebooting in 4 seconds");
+ cli_print(&cli, "Rebooting in 3 seconds");
HAL_Delay(3000);
HAL_NVIC_SystemReset();
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 17:55:48 +0000