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authorFredrik Thulin <fredrik@thulin.net>2016-05-18 21:14:52 +0200
committerFredrik Thulin <fredrik@thulin.net>2016-05-18 21:14:52 +0200
commit523d1f66453e9b92835ecc661085e4575426e661 (patch)
tree008ff6e22deeecbcb6fc9571db1fd7ecce306ea1 /projects/rtos-test/Makefile
parent5e32bc524c4987cfe33cccdb544e3f8d66802895 (diff)
Add FPGA bitstream upload command to cli-test.
This code needs more error checking etc. but together with the Python script 'filetransfer', a new bitstream may be loaded into the FPGA config memory like this: filetransfer --fpga /path/to/bitstream The bitstream is identified by 'file' e.g. like this: alpha_test_top.bit: Xilinx BIT data - from alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built 2016/05/12(13:59:24) - data length 0xe0164
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