SDRAM initialization and test code from Pavel.

Integrated into the cli-test program as such:

cryptech> test sdram
Initializing SDRAM
Starting SDRAM test (n = 0)
Run sequential write-then-read test for the first chip
Run random write-then-read test for the first chip
Run sequential write-then-read test for the second chip
Run random write-then-read test for the second chip
Run interleaved write-then-read test for both chips at once
SDRAM test (n = 0) completed
SDRAM test completed successfully

cryptech>

6 files changed, 417 insertions, 36 deletions

diff --git a/projects/cli-test/Makefile b/projects/cli-test/Makefile
index f3976e4..7737e13 100644
--- a/projects/cli-test/Makefile
+++ b/projects/cli-test/Makefile
@@ -1,6 +1,6 @@
 TEST = cli-test
 
-OBJS = crc32.o mgmt-cli.o
+OBJS = crc32.o mgmt-cli.o test_sdram.o
 
 CFLAGS += -I$(LIBCLI_DIR)
 LIBS += $(LIBCLI_DIR)/libcli.a
diff --git a/projects/cli-test/cli-test.c b/projects/cli-test/cli-test.c
index 152c121..dfcf856 100644
--- a/projects/cli-test/cli-test.c
+++ b/projects/cli-test/cli-test.c
@@ -37,38 +37,12 @@
 #include "stm-uart.h"
 #include "stm-fpgacfg.h"
 #include "stm-keystore.h"
+#include "stm-sdram.h"
 #include "mgmt-cli.h"
+#include "test_sdram.h"
 
 #include <string.h>
 
-/* A bunch of defines to make it easier to add/maintain the CLI commands.
- *
- */
-#define _cli_cmd_struct(name, fullname, func, help)		\
-    static struct cli_command cmd_##fullname##_s =		\
-	{(char *) #name, func, 0, help,				\
-	 PRIVILEGE_UNPRIVILEGED, MODE_EXEC, NULL, NULL, NULL}
-
-/* ROOT is a top-level label with no command */
-#define cli_command_root(name)					\
-    _cli_cmd_struct(name, name, NULL, NULL);			\
-    cli_register_command2(cli, &cmd_##name##_s, NULL)
-
-/* BRANCH is a label with a parent, but no command */
-#define cli_command_branch(parent, name)				\
-    _cli_cmd_struct(name, parent##_##name, NULL, NULL);			\
-    cli_register_command2(cli, &cmd_##parent##_##name##_s, &cmd_##parent##_s)
-
-/* NODE is a label with a parent and with a command associated with it */
-#define cli_command_node(parent, name, help)				\
-    _cli_cmd_struct(name, parent##_##name, cmd_##parent##_##name, (char *) help); \
-    cli_register_command2(cli, &cmd_##parent##_##name##_s, &cmd_##parent##_s)
-
-/* ROOT NODE is a label without a parent, but with a command associated with it */
-#define cli_command_root_node(name, help)				\
-    _cli_cmd_struct(name, name, NULL, (char *) help);			\
-    cli_register_command2(cli, &cmd_##name##_s, NULL)
-
 
 extern uint32_t update_crc(uint32_t crc, uint8_t *buf, int len);
 
@@ -306,6 +280,64 @@ int cmd_reboot(struct cli_def *cli, const char *command, char *argv[], int argc)
     while (1) {};
 }
 
+int cmd_test_sdram(struct cli_def *cli, const char *command, char *argv[], int argc)
+{
+    // run external memory initialization sequence
+    HAL_StatusTypeDef status;
+    int ok, n = 1, test_completed;
+
+    cli_print(cli, "Initializing SDRAM");
+    status = sdram_init();
+    if (status != HAL_OK) {
+	cli_print(cli, "Failed initializing SDRAM: %i", (int) status);
+	return CLI_OK;
+    }
+
+    /* XXX support number of iterations given as argument like 'test sdram 5' */
+    while (n--) {
+	cli_print(cli, "Starting SDRAM test (n = %i)", n);
+	test_completed = 0;
+	// set LFSRs to some initial value, LFSRs will produce
+	// pseudo-random 32-bit patterns to test our memories
+	lfsr1 = 0xCCAA5533;
+	lfsr2 = 0xCCAA5533;
+
+	cli_print(cli, "Run sequential write-then-read test for the first chip");
+	ok = test_sdram_sequential(SDRAM_BASEADDR_CHIP1);
+	if (!ok) break;
+
+	cli_print(cli, "Run random write-then-read test for the first chip");
+	ok = test_sdram_random(SDRAM_BASEADDR_CHIP1);
+	if (!ok) break;
+
+	cli_print(cli, "Run sequential write-then-read test for the second chip");
+	ok = test_sdram_sequential(SDRAM_BASEADDR_CHIP2);
+	if (!ok) break;
+
+	cli_print(cli, "Run random write-then-read test for the second chip");
+	ok = test_sdram_random(SDRAM_BASEADDR_CHIP2);
+	if (!ok) break;
+
+	// turn blue led on (testing two chips at the same time)
+	led_on(LED_BLUE);
+
+	cli_print(cli, "Run interleaved write-then-read test for both chips at once");
+	ok = test_sdrams_interleaved(SDRAM_BASEADDR_CHIP1, SDRAM_BASEADDR_CHIP2);
+
+	led_off(LED_BLUE);
+	test_completed = 1;
+	cli_print(cli, "SDRAM test (n = %i) completed", n);
+    }
+
+    if (! test_completed) {
+	cli_print(cli, "SDRAM test failed (n = %i)", n);
+    } else {
+	cli_print(cli, "SDRAM test completed successfully");
+    }
+
+    return CLI_OK;
+}
+
 int check_auth(const char *username, const char *password)
 {
     if (strcasecmp(username, "ct") != 0)
@@ -349,6 +381,15 @@ void configure_cli_fpga(struct cli_def *cli)
     cli_command_node(fpga_bitstream, erase, "Erase FPGA config memory");
 }
 
+void configure_cli_test(struct cli_def *cli)
+{
+    /* test */
+    cli_command_root(test);
+
+    /* test sdram */
+    cli_command_node(test, sdram, "Run SDRAM tests");
+}
+
 void configure_cli_misc(struct cli_def *cli)
 {
     /* filetransfer */
@@ -371,6 +412,7 @@ main()
 
     configure_cli_show(&cli);
     configure_cli_fpga(&cli);
+    configure_cli_test(&cli);
     configure_cli_misc(&cli);
 
     led_off(LED_RED);
diff --git a/projects/cli-test/mgmt-cli.c b/projects/cli-test/mgmt-cli.c
index 8d53515..faaafda 100644
--- a/projects/cli-test/mgmt-cli.c
+++ b/projects/cli-test/mgmt-cli.c
@@ -33,7 +33,6 @@
  */
 #include "stm32f4xx_hal.h"
 #include "stm-init.h"
-#include "stm-led.h"
 #include "stm-uart.h"
 #include "mgmt-cli.h"
 
@@ -79,11 +78,8 @@ int embedded_cli_loop(struct cli_def *cli)
 
     while (1) {
 	cli_loop_start_new_command(cli, &ctx);
-	HAL_GPIO_TogglePin(LED_PORT, LED_YELLOW);
 
 	while (1) {
-	    HAL_GPIO_TogglePin(LED_PORT, LED_BLUE);
-
 	    cli_loop_show_prompt(cli, &ctx);
 
 	    n = cli_loop_read_next_char(cli, &ctx, &c);
diff --git a/projects/cli-test/mgmt-cli.h b/projects/cli-test/mgmt-cli.h
index 2f1f139..e6780a3 100644
--- a/projects/cli-test/mgmt-cli.h
+++ b/projects/cli-test/mgmt-cli.h
@@ -38,13 +38,40 @@
 #include "stm32f4xx_hal.h"
 #include <libcli.h>
 
+
+/* A bunch of defines to make it easier to add/maintain the CLI commands.
+ *
+ */
+#define _cli_cmd_struct(name, fullname, func, help)		\
+    static struct cli_command cmd_##fullname##_s =		\
+	{(char *) #name, func, 0, help,				\
+	 PRIVILEGE_UNPRIVILEGED, MODE_EXEC, NULL, NULL, NULL}
+
+/* ROOT is a top-level label with no command */
+#define cli_command_root(name)					\
+    _cli_cmd_struct(name, name, NULL, NULL);			\
+    cli_register_command2(cli, &cmd_##name##_s, NULL)
+
+/* BRANCH is a label with a parent, but no command */
+#define cli_command_branch(parent, name)				\
+    _cli_cmd_struct(name, parent##_##name, NULL, NULL);			\
+    cli_register_command2(cli, &cmd_##parent##_##name##_s, &cmd_##parent##_s)
+
+/* NODE is a label with a parent and with a command associated with it */
+#define cli_command_node(parent, name, help)				\
+    _cli_cmd_struct(name, parent##_##name, cmd_##parent##_##name, (char *) help); \
+    cli_register_command2(cli, &cmd_##parent##_##name##_s, &cmd_##parent##_s)
+
+/* ROOT NODE is a label without a parent, but with a command associated with it */
+#define cli_command_root_node(name, help)				\
+    _cli_cmd_struct(name, name, NULL, (char *) help);			\
+    cli_register_command2(cli, &cmd_##name##_s, NULL)
+
+
 extern void uart_cli_print(struct cli_def *cli __attribute__ ((unused)), const char *buf);
 extern int uart_cli_read(struct cli_def *cli __attribute__ ((unused)), void *buf, size_t count);
 extern int uart_cli_write(struct cli_def *cli __attribute__ ((unused)), const void *buf, size_t count);
 extern int embedded_cli_loop(struct cli_def *cli);
 extern void mgmt_cli_init(struct cli_def *cli);
 
-extern __IO ITStatus MgmtUartDataReceived;
-extern __IO ITStatus MgmtUartShouldCli;
-
 #endif /* __STM32_MGMT_CLI_H */
diff --git a/projects/cli-test/test_sdram.c b/projects/cli-test/test_sdram.c
new file mode 100644
index 0000000..e720667
--- /dev/null
+++ b/projects/cli-test/test_sdram.c
@@ -0,0 +1,274 @@
+/*

+ * test_sdram.c

+ * ------------

+ * Test code for the 2x512 MBit SDRAM working memory.

+ *

+ * Copyright (c) 2016, NORDUnet A/S All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are

+ * met:

+ * - Redistributions of source code must retain the above copyright notice,

+ *   this list of conditions and the following disclaimer.

+ *

+ * - Redistributions in binary form must reproduce the above copyright

+ *   notice, this list of conditions and the following disclaimer in the

+ *   documentation and/or other materials provided with the distribution.

+ *

+ * - Neither the name of the NORDUnet nor the names of its contributors may

+ *   be used to endorse or promote products derived from this software

+ *   without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS

+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED

+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED

+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+ */

+#include "stm32f4xx_hal.h"

+#include "stm-led.h"

+#include "stm-sdram.h"

+#include "test_sdram.h"

+

+

+uint32_t lfsr1;

+uint32_t lfsr2;

+

+

+int test_sdram_sequential(uint32_t *base_addr)

+{

+    // memory offset

+    int offset;

+

+    // readback value

+    uint32_t sdram_readback;

+

+

+    /* This test fills entire memory chip with some pseudo-random pattern

+       starting from the very first cell and going in linear fashion. It then

+       reads entire memory and compares read values with what was written. */

+

+

+    // turn on yellow led to indicate, that we're writing

+    led_on(LED_YELLOW);

+

+

+    //

+    // Note, that SDRAM_SIZE is in BYTES, and since we write using

+    // 32-bit words, total number of words is SDRAM_SIZE / 4.

+    //

+

+    // fill entire memory with "random" values

+    for (offset=0; offset<(SDRAM_SIZE >> 2); offset++)	{

+	// generate next "random" value to write

+	lfsr1 = lfsr_next_32(lfsr1);

+

+	// write to memory

+	base_addr[offset] = lfsr1;

+    }

+

+

+    // turn off yellow led to indicate, that we're going to read

+    led_off(LED_YELLOW);

+

+

+    // read entire memory and compare values

+    for (offset=0; offset<(SDRAM_SIZE >> 2); offset++)	{

+	// generate next "random" value (we use the second LFSR to catch up)

+	lfsr2 = lfsr_next_32(lfsr2);

+

+	// read from memory

+	sdram_readback = base_addr[offset];

+

+	// compare and abort test in case of mismatch

+	if (sdram_readback != lfsr2) return 0;

+    }

+

+    // done

+    return 1;

+}

+

+

+//-----------------------------------------------------------------------------

+int test_sdram_random(uint32_t *base_addr)

+//-----------------------------------------------------------------------------

+{

+    // cell counter, memory offset

+    int counter, offset;

+

+    // readback value

+    uint32_t sdram_readback;

+

+

+    /* This test fills entire memory chip with some pseudo-random pattern

+       starting from the very first cell, but then jumping around in pseudo-

+       random fashion to make sure, that SDRAM controller in STM32 handles

+       bank, row and column switching correctly. It then reads entire memory

+       and compares read values with what was written. */

+

+

+    // turn on yellow led to indicate, that we're writing

+    led_on(LED_YELLOW);

+

+

+    //

+    // Note, that SDRAM_SIZE is in BYTES, and since we write using

+    // 32-bit words, total number of words is SDRAM_SIZE / 4.

+    //

+

+    // start with the first cell

+    for (counter=0, offset=0; counter<(SDRAM_SIZE >> 2); counter++)	{

+	// generate next "random" value to write

+	lfsr1 = lfsr_next_32(lfsr1);

+

+	// write to memory

+	base_addr[offset] = lfsr1;

+

+	// generate next "random" address

+

+	//

+	// Note, that for 64 MB memory with 32-bit data bus we need 24 bits

+	// of address, so we use 24-bit LFSR here. Since LFSR has only 2^^24-1

+	// states, i.e. all possible 24-bit values excluding 0, we have to

+	// manually kick it into some arbitrary state during the first iteration.

+	//

+

+	offset = offset ? lfsr_next_24(offset) : 0x00DEC0DE;

+    }

+

+

+    // turn off yellow led to indicate, that we're going to read

+    led_off(LED_YELLOW);

+

+

+    // read entire memory and compare values

+    for (counter=0, offset=0; counter<(SDRAM_SIZE >> 2); counter++) {

+	// generate next "random" value (we use the second LFSR to catch up)

+	lfsr2 = lfsr_next_32(lfsr2);

+

+	// read from memory

+	sdram_readback = base_addr[offset];

+

+	// compare and abort test in case of mismatch

+	if (sdram_readback != lfsr2) return 0;

+

+	// generate next "random" address

+	offset = offset ? lfsr_next_24(offset) : 0x00DEC0DE;

+    }

+

+    //

+    // we should have walked exactly 2**24 iterations and returned

+    // back to the arbitrary starting address...

+    //

+

+    if (offset != 0x00DEC0DE) return 0;

+

+

+    // done

+    return 1;

+}

+

+

+//-----------------------------------------------------------------------------

+int test_sdrams_interleaved(uint32_t *base_addr1, uint32_t *base_addr2)

+//-----------------------------------------------------------------------------

+{

+    // cell counter, memory offsets

+    int counter, offset1, offset2;

+

+    // readback value

+    uint32_t sdram_readback;

+

+

+    /* Basically this is the same as test_sdram_random() except that it

+       tests both memory chips at the same time. */

+

+

+    // turn on yellow led to indicate, that we're writing

+    led_on(LED_YELLOW);

+

+

+    //

+    // Note, that SDRAM_SIZE is in BYTES, and since we write using

+    // 32-bit words, total number of words is SDRAM_SIZE / 4.

+    //

+

+    // start with the first cell

+    for (counter=0, offset1=0, offset2=0; counter<(SDRAM_SIZE >> 2); counter++)	{

+	// generate next "random" value to write

+	lfsr1 = lfsr_next_32(lfsr1);

+

+	// write to memory

+	base_addr1[offset1] = lfsr1;

+	base_addr2[offset2] = lfsr1;

+

+	// generate next "random" addresses (use different starting states!)

+

+	offset1 = offset1 ? lfsr_next_24(offset1) : 0x00ABCDEF;

+	offset2 = offset2 ? lfsr_next_24(offset2) : 0x00FEDCBA;

+    }

+

+

+    // turn off yellow led to indicate, that we're going to read

+    led_off(LED_YELLOW);

+

+

+    // read entire memory and compare values

+    for (counter=0, offset1=0, offset2=0; counter<(SDRAM_SIZE >> 2); counter++)	{

+	// generate next "random" value (we use the second LFSR to catch up)

+	lfsr2 = lfsr_next_32(lfsr2);

+

+	// read from the first memory and compare

+	sdram_readback = base_addr1[offset1];

+	if (sdram_readback != lfsr2) return 0;

+

+	// read from the second memory and compare

+	sdram_readback = base_addr2[offset2];

+	if (sdram_readback != lfsr2) return 0;

+

+	// generate next "random" addresses

+	offset1 = offset1 ? lfsr_next_24(offset1) : 0x00ABCDEF;

+	offset2 = offset2 ? lfsr_next_24(offset2) : 0x00FEDCBA;

+    }

+

+    //

+    // we should have walked exactly 2**24 iterations and returned

+    // back to the arbitrary starting address...

+    //

+

+    if (offset1 != 0x00ABCDEF) return 0;

+    if (offset2 != 0x00FEDCBA) return 0;

+

+    // done

+    return 1;

+}

+

+uint32_t lfsr_next_32(uint32_t lfsr)

+{

+    uint32_t tap = 0;

+

+    tap ^= (lfsr >> 31);

+    tap ^= (lfsr >> 30);

+    tap ^= (lfsr >> 29);

+    tap ^= (lfsr >> 9);

+

+    return (lfsr << 1) | (tap & 1);

+}

+

+uint32_t lfsr_next_24(uint32_t lfsr)

+{

+    unsigned int tap = 0;

+

+    tap ^= (lfsr >> 23);

+    tap ^= (lfsr >> 22);

+    tap ^= (lfsr >> 21);

+    tap ^= (lfsr >> 16);

+

+    return ((lfsr << 1) | (tap & 1)) & 0x00FFFFFF;

+}

diff --git a/projects/cli-test/test_sdram.h b/projects/cli-test/test_sdram.h
new file mode 100644
index 0000000..b848d18
--- /dev/null
+++ b/projects/cli-test/test_sdram.h
@@ -0,0 +1,42 @@
+/*
+ * test_sdram.h
+ * ------------
+ * Prototypes and defines for testing the 2x512 MBit SDRAM working memory.
+ *
+ * Copyright (c) 2016, NORDUnet A/S All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ *
+ * - Neither the name of the NORDUnet nor the names of its contributors may
+ *   be used to endorse or promote products derived from this software
+ *   without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+extern uint32_t lfsr1;
+extern uint32_t lfsr2;
+
+extern int test_sdram_sequential(uint32_t *base_addr);
+extern int test_sdram_random(uint32_t *base_addr);
+extern int test_sdrams_interleaved(uint32_t *base_addr1, uint32_t *base_addr2);
+
+extern uint32_t lfsr_next_32(uint32_t lfsr);
+extern uint32_t lfsr_next_24(uint32_t lfsr);