diff options
| author | Fredrik Thulin <fredrik@thulin.net> | 2016-06-02 14:56:56 +0200 |
|---|---|---|
| committer | Fredrik Thulin <fredrik@thulin.net> | 2016-06-02 14:56:56 +0200 |
| commit | ae1ecf87f6b8d7c34b32af0547f118ff7697c2ef (patch) | |
| tree | ad7923423ba64b3a40f2646b210617340d96eaf2 /projects/cli-test/filetransfer | |
| parent | 1b3870dd4e0429e1809ce40b70a8f558ffb5df3a (diff) | |
Use DMA for UART RX instead of interrupts.
DMA is more efficient and less prone to miss characters than interrupts.
An open question is if circular mode is really the best. If someone
copy-pastes more than the RX buffer size of configuration into the CLI,
we risk the DMA controller catching up with the reader and overwriting
data not yet read.
Since we don't have flow control back to the users terminal, we will
always fail if too much data is entered before we can process it. The
question is if failing to stuff new data at the end of a buffer might be
better than data being overwritten - thus messing up the commands in
unpredictable ways.
Diffstat (limited to 'projects/cli-test/filetransfer')
| -rwxr-xr-x | projects/cli-test/filetransfer | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/projects/cli-test/filetransfer b/projects/cli-test/filetransfer index 025a6ac..f704e31 100755 --- a/projects/cli-test/filetransfer +++ b/projects/cli-test/filetransfer @@ -77,11 +77,9 @@ def parse_args(): def _write(dst, data): - for i in range(len(data)): - dst.write(data[i]) - time.sleep(0.1) + dst.write(data) if len(data) == 4: - print("Wrote 0x{:02x}{:02x}{:02x}{:02x}".format(ord(data[0]), ord(data[1]), ord(data[2]), ord(data[3]))) + print("Wrote 0x{!s}".format(data.encode('hex'))) else: print("Wrote {!r}".format(data)) |