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| author | Fredrik Thulin <fredrik@thulin.net> | 2016-05-18 21:14:52 +0200 |
|---|---|---|
| committer | Fredrik Thulin <fredrik@thulin.net> | 2016-05-18 21:14:52 +0200 |
| commit | 523d1f66453e9b92835ecc661085e4575426e661 (patch) | |
| tree | 008ff6e22deeecbcb6fc9571db1fd7ecce306ea1 /libraries/mbed/targets/cmsis/TARGET_STM | |
| parent | 5e32bc524c4987cfe33cccdb544e3f8d66802895 (diff) | |
Add FPGA bitstream upload command to cli-test.
This code needs more error checking etc. but together with the Python
script 'filetransfer', a new bitstream may be loaded into the FPGA
config memory like this:
filetransfer --fpga /path/to/bitstream
The bitstream is identified by 'file' e.g. like this:
alpha_test_top.bit: Xilinx BIT data - from
alpha_test_top.ncd;UserID=0xFFFFFFFF - for 7a200tfbg484 - built
2016/05/12(13:59:24) - data length 0xe0164
Diffstat (limited to 'libraries/mbed/targets/cmsis/TARGET_STM')
| -rw-r--r-- | libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c index c6a8a67..d0f814e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_CRYPTECH_ALPHA/stm32f4xx_hal_msp.c @@ -216,7 +216,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) GPIO_InitTypeDef GPIO_InitStruct; if (hspi->Instance == SPI2) { /* Peripheral clock enable */ - __HAL_RCC_SPI2_CLK_ENABLE(); + __SPI2_CLK_ENABLE(); /* SPI2 is the FPGA config memory. * |