import mbed rtos library

3 files changed, 0 insertions, 1334 deletions

diff --git a/Device/ldscripts/stm32f429bitx.ld b/Device/ldscripts/stm32f429bitx.ld
deleted file mode 100644
index fd428f4..0000000
--- a/Device/ldscripts/stm32f429bitx.ld
+++ /dev/null
@@ -1,186 +0,0 @@
-/*

-*****************************************************************************

-**

-**  File        : stm32_flash.ld

-**

-**  Abstract    : Linker script for STM32F429BI Device with

-**                2048KByte FLASH, 192KByte RAM

-**

-**                Set heap size, stack size and stack location according

-**                to application requirements.

-**

-**                Set memory bank area and size if external memory is used.

-**

-**  Target      : STMicroelectronics STM32

-**

-**  Environment : Atollic TrueSTUDIO(R)

-**

-**  Distribution: The file is distributed “as is,” without any warranty

-**                of any kind.

-**

-**  (c)Copyright Atollic AB.

-**  You may use this file as-is or modify it according to the needs of your

-**  project. This file may only be built (assembled or compiled and linked)

-**  using the Atollic TrueSTUDIO(R) product. The use of this file together

-**  with other tools than Atollic TrueSTUDIO(R) is not permitted.

-**

-*****************************************************************************

-*/

-

-/* Entry Point */

-ENTRY(Reset_Handler)

-

-/* Highest address of the user mode stack */

-_estack = 0x2002FFFF;    /* end of RAM */

-

-/* Generate a link error if heap and stack don't fit into RAM */

-_Min_Heap_Size = 0;      /* required amount of heap  */

-_Min_Stack_Size = 0x400; /* required amount of stack */

-

-/* Specify the memory areas */

-MEMORY

-{

-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K

-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 192K

-CCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K

-}

-

-/* Define output sections */

-SECTIONS

-{

-  /* The startup code goes first into FLASH */

-  .isr_vector :

-  {

-    . = ALIGN(4);

-    KEEP(*(.isr_vector)) /* Startup code */

-    . = ALIGN(4);

-  } >FLASH

-

-  /* The program code and other data goes into FLASH */

-  .text :

-  {

-    . = ALIGN(4);

-    *(.text)           /* .text sections (code) */

-    *(.text*)          /* .text* sections (code) */

-    *(.glue_7)         /* glue arm to thumb code */

-    *(.glue_7t)        /* glue thumb to arm code */

-    *(.eh_frame)

-

-    KEEP (*(.init))

-    KEEP (*(.fini))

-

-    . = ALIGN(4);

-    _etext = .;        /* define a global symbols at end of code */

-  } >FLASH

-

-  /* Constant data goes into FLASH */

-  .rodata :

-  {

-    . = ALIGN(4);

-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */

-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */

-    . = ALIGN(4);

-  } >FLASH

-

-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH

-  .ARM : {

-    __exidx_start = .;

-    *(.ARM.exidx*)

-    __exidx_end = .;

-  } >FLASH

-

-  .preinit_array     :

-  {

-    PROVIDE_HIDDEN (__preinit_array_start = .);

-    KEEP (*(.preinit_array*))

-    PROVIDE_HIDDEN (__preinit_array_end = .);

-  } >FLASH

-  .init_array :

-  {

-    PROVIDE_HIDDEN (__init_array_start = .);

-    KEEP (*(SORT(.init_array.*)))

-    KEEP (*(.init_array*))

-    PROVIDE_HIDDEN (__init_array_end = .);

-  } >FLASH

-  .fini_array :

-  {

-    PROVIDE_HIDDEN (__fini_array_start = .);

-    KEEP (*(SORT(.fini_array.*)))

-    KEEP (*(.fini_array*))

-    PROVIDE_HIDDEN (__fini_array_end = .);

-  } >FLASH

-

-  /* used by the startup to initialize data */

-  _sidata = LOADADDR(.data);

-

-  /* Initialized data sections goes into RAM, load LMA copy after code */

-  .data : 

-  {

-    . = ALIGN(4);

-    _sdata = .;        /* create a global symbol at data start */

-    *(.data)           /* .data sections */

-    *(.data*)          /* .data* sections */

-

-    . = ALIGN(4);

-    _edata = .;        /* define a global symbol at data end */

-  } >RAM AT> FLASH

-

-  _siccmram = LOADADDR(.ccmram);

-

-  /* CCM-RAM section 

-  * 

-  * IMPORTANT NOTE! 

-  * If initialized variables will be placed in this section, 

-  * the startup code needs to be modified to copy the init-values.  

-  */

-  .ccmram :

-  {

-    . = ALIGN(4);

-    _sccmram = .;       /* create a global symbol at ccmram start */

-    *(.ccmram)

-    *(.ccmram*)

-    

-    . = ALIGN(4);

-    _eccmram = .;       /* create a global symbol at ccmram end */

-  } >CCMRAM AT> FLASH

-

-  

-  /* Uninitialized data section */

-  . = ALIGN(4);

-  .bss :

-  {

-    /* This is used by the startup in order to initialize the .bss secion */

-    _sbss = .;         /* define a global symbol at bss start */

-    __bss_start__ = _sbss;

-    *(.bss)

-    *(.bss*)

-    *(COMMON)

-

-    . = ALIGN(4);

-    _ebss = .;         /* define a global symbol at bss end */

-    __bss_end__ = _ebss;

-  } >RAM

-

-  /* User_heap_stack section, used to check that there is enough RAM left */

-  ._user_heap_stack :

-  {

-    . = ALIGN(4);

-    PROVIDE ( end = . );

-    PROVIDE ( _end = . );

-    . = . + _Min_Heap_Size;

-    . = . + _Min_Stack_Size;

-    . = ALIGN(4);

-  } >RAM

-

-  

-

-  /* Remove information from the standard libraries */

-  /DISCARD/ :

-  {

-    libc.a ( * )

-    libm.a ( * )

-    libgcc.a ( * )

-  }

-

-  .ARM.attributes 0 : { *(.ARM.attributes) }

-}

diff --git a/Device/startup_stm32f429xx.s b/Device/startup_stm32f429xx.s
deleted file mode 100644
index f8ba161..0000000
--- a/Device/startup_stm32f429xx.s
+++ /dev/null
@@ -1,561 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f429xx.s
-  * @author    MCD Application Team
-  * @version   V2.3.2
-  * @date      26-June-2015
-  * @brief     STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m4
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   sp, =_estack       /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2], #4
-
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl  main
-  bx  lr
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None
- * @retval None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  MemManage_Handler
-  .word  BusFault_Handler
-  .word  UsageFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-
-  /* External Interrupts */
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
-  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
-  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
-  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
-  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
-  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
-  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
-  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
-  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
-  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
-  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
-  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
-  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
-  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
-  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
-  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
-  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
-  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
-  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
-  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
-  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
-  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
-  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM4_IRQHandler                   /* TIM4                         */
-  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
-  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
-  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
-  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     USART3_IRQHandler                 /* USART3                       */
-  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
-  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
-  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
-  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
-  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
-  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
-  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
-  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
-  .word     FMC_IRQHandler                    /* FMC                         */
-  .word     SDIO_IRQHandler                   /* SDIO                         */
-  .word     TIM5_IRQHandler                   /* TIM5                         */
-  .word     SPI3_IRQHandler                   /* SPI3                         */
-  .word     UART4_IRQHandler                  /* UART4                        */
-  .word     UART5_IRQHandler                  /* UART5                        */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
-  .word     TIM7_IRQHandler                   /* TIM7                         */
-  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
-  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
-  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
-  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
-  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
-  .word     ETH_IRQHandler                    /* Ethernet                     */
-  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
-  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
-  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
-  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
-  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
-  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
-  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
-  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
-  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
-  .word     USART6_IRQHandler                 /* USART6                       */
-  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
-  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
-  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
-  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
-  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
-  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
-  .word     DCMI_IRQHandler                   /* DCMI                         */
-  .word     0                                 /* Reserved                     */
-  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
-  .word     FPU_IRQHandler                    /* FPU                          */
-  .word     UART7_IRQHandler                  /* UART7                        */
-  .word     UART8_IRQHandler                  /* UART8                        */
-  .word     SPI4_IRQHandler                   /* SPI4                         */
-  .word     SPI5_IRQHandler                   /* SPI5 						  */
-  .word     SPI6_IRQHandler                   /* SPI6						  */
-  .word     SAI1_IRQHandler                   /* SAI1						  */
-  .word     LTDC_IRQHandler                   /* LTDC_IRQHandler			  */
-  .word     LTDC_ER_IRQHandler                /* LTDC_ER_IRQHandler			  */
-  .word     DMA2D_IRQHandler                  /* DMA2D                        */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      MemManage_Handler
-   .thumb_set MemManage_Handler,Default_Handler
-
-   .weak      BusFault_Handler
-   .thumb_set BusFault_Handler,Default_Handler
-
-   .weak      UsageFault_Handler
-   .thumb_set UsageFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      DebugMon_Handler
-   .thumb_set DebugMon_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      TAMP_STAMP_IRQHandler
-   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
-   .weak      RTC_WKUP_IRQHandler
-   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_IRQHandler
-   .thumb_set EXTI0_IRQHandler,Default_Handler
-
-   .weak      EXTI1_IRQHandler
-   .thumb_set EXTI1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_IRQHandler
-   .thumb_set EXTI2_IRQHandler,Default_Handler
-
-   .weak      EXTI3_IRQHandler
-   .thumb_set EXTI3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_IRQHandler
-   .thumb_set EXTI4_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream0_IRQHandler
-   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream1_IRQHandler
-   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream2_IRQHandler
-   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream3_IRQHandler
-   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream4_IRQHandler
-   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream5_IRQHandler
-   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream6_IRQHandler
-   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
-   .weak      ADC_IRQHandler
-   .thumb_set ADC_IRQHandler,Default_Handler
-
-   .weak      CAN1_TX_IRQHandler
-   .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
-   .weak      CAN1_RX0_IRQHandler
-   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
-   .weak      CAN1_RX1_IRQHandler
-   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
-   .weak      CAN1_SCE_IRQHandler
-   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
-   .weak      EXTI9_5_IRQHandler
-   .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-   .weak      TIM1_BRK_TIM9_IRQHandler
-   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
-   .weak      TIM1_UP_TIM10_IRQHandler
-   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
-   .weak      TIM1_TRG_COM_TIM11_IRQHandler
-   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
-   .weak      TIM1_CC_IRQHandler
-   .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM4_IRQHandler
-   .thumb_set TIM4_IRQHandler,Default_Handler
-
-   .weak      I2C1_EV_IRQHandler
-   .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-   .weak      I2C1_ER_IRQHandler
-   .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-   .weak      I2C2_EV_IRQHandler
-   .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-   .weak      I2C2_ER_IRQHandler
-   .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      USART3_IRQHandler
-   .thumb_set USART3_IRQHandler,Default_Handler
-
-   .weak      EXTI15_10_IRQHandler
-   .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-   .weak      RTC_Alarm_IRQHandler
-   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-   .weak      OTG_FS_WKUP_IRQHandler
-   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
-   .weak      TIM8_BRK_TIM12_IRQHandler
-   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
-   .weak      TIM8_UP_TIM13_IRQHandler
-   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
-   .weak      TIM8_TRG_COM_TIM14_IRQHandler
-   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
-   .weak      TIM8_CC_IRQHandler
-   .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Stream7_IRQHandler
-   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
-   .weak      FMC_IRQHandler
-   .thumb_set FMC_IRQHandler,Default_Handler
-
-   .weak      SDIO_IRQHandler
-   .thumb_set SDIO_IRQHandler,Default_Handler
-
-   .weak      TIM5_IRQHandler
-   .thumb_set TIM5_IRQHandler,Default_Handler
-
-   .weak      SPI3_IRQHandler
-   .thumb_set SPI3_IRQHandler,Default_Handler
-
-   .weak      UART4_IRQHandler
-   .thumb_set UART4_IRQHandler,Default_Handler
-
-   .weak      UART5_IRQHandler
-   .thumb_set UART5_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream0_IRQHandler
-   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream1_IRQHandler
-   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream2_IRQHandler
-   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream3_IRQHandler
-   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream4_IRQHandler
-   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
-   .weak      ETH_IRQHandler
-   .thumb_set ETH_IRQHandler,Default_Handler
-
-   .weak      ETH_WKUP_IRQHandler
-   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
-   .weak      CAN2_TX_IRQHandler
-   .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
-   .weak      CAN2_RX0_IRQHandler
-   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
-   .weak      CAN2_RX1_IRQHandler
-   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
-   .weak      CAN2_SCE_IRQHandler
-   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
-   .weak      OTG_FS_IRQHandler
-   .thumb_set OTG_FS_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream5_IRQHandler
-   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream6_IRQHandler
-   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
-   .weak      DMA2_Stream7_IRQHandler
-   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
-   .weak      USART6_IRQHandler
-   .thumb_set USART6_IRQHandler,Default_Handler
-
-   .weak      I2C3_EV_IRQHandler
-   .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
-   .weak      I2C3_ER_IRQHandler
-   .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
-   .weak      OTG_HS_EP1_OUT_IRQHandler
-   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
-   .weak      OTG_HS_EP1_IN_IRQHandler
-   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
-   .weak      OTG_HS_WKUP_IRQHandler
-   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
-   .weak      OTG_HS_IRQHandler
-   .thumb_set OTG_HS_IRQHandler,Default_Handler
-
-   .weak      DCMI_IRQHandler
-   .thumb_set DCMI_IRQHandler,Default_Handler
-
-   .weak      HASH_RNG_IRQHandler
-   .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
-   .weak      FPU_IRQHandler
-   .thumb_set FPU_IRQHandler,Default_Handler
-
-   .weak      UART7_IRQHandler
-   .thumb_set UART7_IRQHandler,Default_Handler
-
-   .weak      UART8_IRQHandler
-   .thumb_set UART8_IRQHandler,Default_Handler
-
-   .weak      SPI4_IRQHandler
-   .thumb_set SPI4_IRQHandler,Default_Handler
-
-   .weak      SPI5_IRQHandler
-   .thumb_set SPI5_IRQHandler,Default_Handler
-
-   .weak      SPI6_IRQHandler
-   .thumb_set SPI6_IRQHandler,Default_Handler
-
-   .weak      SAI1_IRQHandler
-   .thumb_set SAI1_IRQHandler,Default_Handler
-
-   .weak      LTDC_IRQHandler
-   .thumb_set LTDC_IRQHandler,Default_Handler
-
-   .weak      LTDC_ER_IRQHandler
-   .thumb_set LTDC_ER_IRQHandler,Default_Handler
-
-   .weak      DMA2D_IRQHandler
-   .thumb_set DMA2D_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
diff --git a/Device/system_stm32f4xx.c b/Device/system_stm32f4xx.c
deleted file mode 100644
index bc78fb2..0000000
--- a/Device/system_stm32f4xx.c
+++ /dev/null
@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f4xx.c
-  * @author  MCD Application Team
-  * @version V2.3.2
-  * @date    26-June-2015
-  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f4xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Includes
-  * @{
-  */
-
-
-#include "stm32f4xx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
-  * @{
-  */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx)
-/* #define DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
-
-#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
- #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
-#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock = 16000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the FPU setting, vector table location and External memory
-  *         configuration.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
-  #endif
-  /* Reset the RCC clock configuration to the default reset state ------------*/
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset CFGR register */
-  RCC->CFGR = 0x00000000;
-
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset PLLCFGR register */
-  RCC->PLLCFGR = 0x24003010;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-  SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
-   * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
-  *              depends on the application requirements), user has to ensure that HSE_VALUE
-  *              is same as the real frequency of the crystal used. Otherwise, this function
-  *              may have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock source */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock source */
-
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
-         SYSCLK = PLL_VCO / PLL_P
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
-      if (pllsource != 0)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
-      }
-
-      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
-      SystemCoreClock = pllvco/pllp;
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK frequency --------------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in startup_stm32f4xx.s before jump to main.
-  *         This function configures the external memories (SRAM/SDRAM)
-  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-  __IO uint32_t tmp = 0x00;
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
-#if defined (DATA_IN_ExtSDRAM)
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
-  register uint32_t index;
-
-#if defined(STM32F446xx)
-  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
-      clock */
-  RCC->AHB1ENR |= 0x0000007D;
-#else
-  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
-      clock */
-  RCC->AHB1ENR |= 0x000001F8;
-#endif /* STM32F446xx */
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
-
-#if defined(STM32F446xx)
-  /* Connect PAx pins to FMC Alternate function */
-  GPIOA->AFR[0]  |= 0xC0000000;
-  GPIOA->AFR[1]  |= 0x00000000;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOA->MODER   |= 0x00008000;
-  /* Configure PDx pins speed to 50 MHz */
-  GPIOA->OSPEEDR |= 0x00008000;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOA->OTYPER  |= 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOA->PUPDR   |= 0x00000000;
-
-  /* Connect PCx pins to FMC Alternate function */
-  GPIOC->AFR[0]  |= 0x00CC0000;
-  GPIOC->AFR[1]  |= 0x00000000;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOC->MODER   |= 0x00000A00;
-  /* Configure PDx pins speed to 50 MHz */
-  GPIOC->OSPEEDR |= 0x00000A00;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOC->OTYPER  |= 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOC->PUPDR   |= 0x00000000;
-#endif /* STM32F446xx */
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x000000CC;
-  GPIOD->AFR[1]  = 0xCC000CCC;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOD->MODER   = 0xA02A000A;
-  /* Configure PDx pins speed to 50 MHz */
-  GPIOD->OSPEEDR = 0xA02A000A;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 50 MHz */
-  GPIOE->OSPEEDR = 0xAAAA800A;
-  /* Configure PEx pins Output type to push-pull */
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0xCCCCCCCC;
-  GPIOF->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PFx pins in Alternate function mode */
-  GPIOF->MODER   = 0xAA800AAA;
-  /* Configure PFx pins speed to 50 MHz */
-  GPIOF->OSPEEDR = 0xAA800AAA;
-  /* Configure PFx pins Output type to push-pull */
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0xCCCCCCCC;
-  GPIOG->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PGx pins in Alternate function mode */
-  GPIOG->MODER   = 0xAAAAAAAA;
-  /* Configure PGx pins speed to 50 MHz */
-  GPIOG->OSPEEDR = 0xAAAAAAAA;
-  /* Configure PGx pins Output type to push-pull */
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
-  GPIOG->PUPDR   = 0x00000000;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-  /* Connect PHx pins to FMC Alternate function */
-  GPIOH->AFR[0]  = 0x00C0CC00;
-  GPIOH->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PHx pins in Alternate function mode */
-  GPIOH->MODER   = 0xAAAA08A0;
-  /* Configure PHx pins speed to 50 MHz */
-  GPIOH->OSPEEDR = 0xAAAA08A0;
-  /* Configure PHx pins Output type to push-pull */
-  GPIOH->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PHx pins */
-  GPIOH->PUPDR   = 0x00000000;
-
-  /* Connect PIx pins to FMC Alternate function */
-  GPIOI->AFR[0]  = 0xCCCCCCCC;
-  GPIOI->AFR[1]  = 0x00000CC0;
-  /* Configure PIx pins in Alternate function mode */
-  GPIOI->MODER   = 0x0028AAAA;
-  /* Configure PIx pins speed to 50 MHz */
-  GPIOI->OSPEEDR = 0x0028AAAA;
-  /* Configure PIx pins Output type to push-pull */
-  GPIOI->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PIx pins */
-  GPIOI->PUPDR   = 0x00000000;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-/*-- FMC Configuration -------------------------------------------------------*/
-  /* Enable the FMC interface clock */
-  RCC->AHB3ENR |= 0x00000001;
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-
-  /* Configure and enable SDRAM bank1 */
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCR[0] = 0x00001954;
-#else
-  FMC_Bank5_6->SDCR[0] = 0x000019E4;
-#endif /* STM32F446xx */
-  FMC_Bank5_6->SDTR[0] = 0x01115351;
-
-  /* SDRAM initialization sequence */
-  /* Clock enable command */
-  FMC_Bank5_6->SDCMR = 0x00000011;
-  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Delay */
-  for (index = 0; index<1000; index++);
-
-  /* PALL command */
-  FMC_Bank5_6->SDCMR = 0x00000012;
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Auto refresh command */
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCMR = 0x000000F3;
-#else
-  FMC_Bank5_6->SDCMR = 0x00000073;
-#endif /* STM32F446xx */
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* MRD register program */
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDCMR = 0x00044014;
-#else
-  FMC_Bank5_6->SDCMR = 0x00046014;
-#endif /* STM32F446xx */
-  timeout = 0xFFFF;
-  while((tmpreg != 0) && (timeout-- > 0))
-  {
-    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
-  }
-
-  /* Set refresh count */
-  tmpreg = FMC_Bank5_6->SDRTR;
-#if defined(STM32F446xx)
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
-#else
-  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
-#endif /* STM32F446xx */
-
-  /* Disable write protection */
-  tmpreg = FMC_Bank5_6->SDCR[0];
-  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-#endif /* DATA_IN_ExtSDRAM */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
-#if defined(DATA_IN_ExtSRAM)
-/*-- GPIOs Configuration -----------------------------------------------------*/
-   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHB1ENR   |= 0x00000078;
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-
-  /* Connect PDx pins to FMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CCC0CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */
-  GPIOD->MODER   = 0xAAAA0A8A;
-  /* Configure PDx pins speed to 100 MHz */
-  GPIOD->OSPEEDR = 0xFFFF0FCF;
-  /* Configure PDx pins Output type to push-pull */
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00CC0CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */
-  GPIOE->MODER   = 0xAAAA828A;
-  /* Configure PEx pins speed to 100 MHz */
-  GPIOE->OSPEEDR = 0xFFFFC3CF;
-  /* Configure PEx pins Output type to push-pull */
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 100 MHz */
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x000000C0;
-  /* Configure PGx pins in Alternate function mode */
-  GPIOG->MODER   = 0x00085AAA;
-  /* Configure PGx pins speed to 100 MHz */
-  GPIOG->OSPEEDR = 0x000CAFFF;
-  /* Configure PGx pins Output type to push-pull */
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */
-  GPIOG->PUPDR   = 0x00000000;
-
-/*-- FMC/FSMC Configuration --------------------------------------------------*/
-  /* Enable the FMC/FSMC interface clock */
-  RCC->AHB3ENR         |= 0x00000001;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
-  /* Configure and enable Bank1_SRAM2 */
-  FMC_Bank1->BTCR[2]  = 0x00001011;
-  FMC_Bank1->BTCR[3]  = 0x00000201;
-  FMC_Bank1E->BWTR[2] = 0x0fffffff;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
-  /* Delay after an RCC peripheral clock enabling */
-  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
-  /* Configure and enable Bank1_SRAM2 */
-  FSMC_Bank1->BTCR[2]  = 0x00001011;
-  FSMC_Bank1->BTCR[3]  = 0x00000201;
-  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-  (void)(tmp);
-}
-#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/