STM32 software for dev-bridge board
===================================
The dev-bridge board is a daughterboard for the Novena, which talks to the
Novena's FPGA through the high-speed expansion connector.
See user/ft/stm32-dev-bridge/hardware/rev01 for schematics of the bridge
board. There will be more information on the wiki shortly.
Copyrights
==========
The license for all work done on this in the CrypTech project is a
3-clause BSD license (see LICENSE.txt for details). Some files have
been generated using the STMicroelectronics initialization code
generator STM32CubeMX and thus have additional copyright header(s).
The "Noise generator" and "Amplifier" parts of the circuit diagram are
copied from Benedikt Stockebrand's ARRGH project. ARRGH copyright
statement is included in LICENSE.txt.
A stripped down copy of the ARM CMSIS library version 3.20 is included
in the Drivers/CMSIS/ directory. Unused parts (and documentation etc.)
have been removed, but every attempt have been made to keep any
licensing information intact. See in particular the file
Drivers/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf.
A full copy of the STM32F4xx HAL Drivers is included in the
Drivers/STM32F4xx_HAL_Driver/ directory.
Building
========
The following packages need to be installed (on Ubuntu 14.04):
apt-get install gcc-arm-none-eabi gdb-arm-none-eabi openocd
To build the source code, issue "make" from the top level directory
(where this file is). The first time, this will build the complete STM
CMSIS library. A subsequent "make clean" will *not* clean away the CMSIS
library, but a "make distclean" will.
Installing
==========
Do "bin/flash-target" from the top level directory (where this file is)
to flash a built image into the microcontroller. See the section ST-LINK
below for information about the actual hardware programming device needed.
ST-LINK
=======
To program the MCU, an ST-LINK adapter is used. The cheapest way to get
one is to buy an evaluation board with an ST-LINK integrated, and pinouts
to program external chips. This should work with any evaluation board from
STM; we have tested with STM32F4DISCOVERY (with ST-LINK v2.0) and
NUCLEO-F411RE (with ST-LINK v2.1).
The ST-LINK programming pins are the 1+4 throughole pads above the ARM
on the circuit board. See the schematics for details, but the pinout
from left to right (1, space, 4) of rev01 is
NRST, space, CLK, IO, GND, VCC
First remove the pair of ST-LINK jumpers (CN4 on the DISCO, CN2 on the
NUCLEO). Then find the 6-pin SWD header on the left of the STM board (CN2
on the DISCO, CN4 on the NUCLEO), and connect them to the dev-bridge
board:
* 5 T_NRST <-> NRST
* 2 T_JTCK <-> CLK
* 4 T_JTMS <-> IO
* 3 GND <-> GND
The dev-bridge board should be connected to the Novena and powered on
before attempting to flash it.
Debugging the firmware
======================
This site shows several ways to use various debuggers to debug the
firmware in an STM32:
http://fun-tech.se/stm32/OpenOCD/gdb.php
I've only managed to get the most basic text line gdb to work,
something along these lines:
1) Start OpenOCD server (with a configuration file for your type of ST-LINK
adapter)
$ openocd -f /usr/share/openocd/scripts/board/stm32f4discovery.cfg
2) Connect to the OpenOCD server and re-flash already compiled firmware:
$ telnet localhost 4444
reset halt
flash probe 0
stm32f2x mass_erase 0
flash write_bank 0 /path/to/main.bin 0
reset halt
3) Start GDB and have it connect to the OpenOCD server:
$ arm-none-eabi-gdb --eval-command="target remote localhost:3333" main.elf
|
/*
* stm-fpgacfg.h
* ---------
* Functions and defines for accessing the FPGA config memory.
*
* Copyright (c) 2016, NORDUnet A/S All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* - Neither the name of the NORDUnet nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __STM32_FPGACFG_H
#define __STM32_FPGACFG_H
#include "stm32f4xx_hal.h"
#define N25Q128_SPI_HANDLE (&hspi_fpgacfg)
#define N25Q128_COMMAND_READ_ID 0x9E
#define N25Q128_COMMAND_READ_PAGE 0x03
#define N25Q128_COMMAND_READ_STATUS 0x05
#define N25Q128_COMMAND_WRITE_ENABLE 0x06
#define N25Q128_COMMAND_ERASE_SECTOR 0xD8
#define N25Q128_COMMAND_PAGE_PROGRAM 0x02
#define N25Q128_PAGE_SIZE 0x100 // 256
#define N25Q128_NUM_PAGES 0x10000 // 65536
#define N25Q128_SECTOR_SIZE 0x10000 // 65536
#define N25Q128_NUM_SECTORS 0x100 // 256
#define N25Q128_SPI_TIMEOUT 1000
#define N25Q128_ID_MANUFACTURER 0x20
#define N25Q128_ID_DEVICE_TYPE 0xBA
#define N25Q128_ID_DEVICE_CAPACITY 0x18
#define PROM_FPGA_DIS_Pin GPIO_PIN_14
#define PROM_FPGA_DIS_GPIO_Port GPIOI
#define PROM_ARM_ENA_Pin GPIO_PIN_6
#define PROM_ARM_ENA_GPIO_Port GPIOF
#define PROM_CS_N_Pin GPIO_PIN_12
#define PROM_CS_N_GPIO_Port GPIOB
#define _n25q128_select() HAL_GPIO_WritePin(PROM_CS_N_GPIO_Port, PROM_CS_N_Pin, GPIO_PIN_RESET);
#define _n25q128_deselect() HAL_GPIO_WritePin(PROM_CS_N_GPIO_Port, PROM_CS_N_Pin, GPIO_PIN_SET);
extern int n25q128_check_id(void);
extern int n25q128_get_wip_flag(void);
extern int n25q128_read_page(uint32_t page_offset, uint8_t *page_buffer);
extern int n25q128_write_page(uint32_t page_offset, uint8_t *page_buffer);
extern int n25q128_erase_sector(uint32_t sector_offset);
extern SPI_HandleTypeDef hspi_fpgacfg;
#endif /* __STM32_FPGACFG_H */
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