/** ****************************************************************************** * @file stm32f4xx_hal_spi.c * @author MCD Application Team * @version V1.4.1 * @date 09-October-2015 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions * + Peripheral State functions @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The SPI HAL driver can be used as follows: (#) Declare a SPI_HandleTypeDef handle structure, for example: SPI_HandleTypeDef hspi; (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: (##) Enable the SPIx interface clock (##) SPI pins configuration (+++) Enable the clock for the SPI GPIOs (+++) Configure these SPI pins as alternate function push-pull (##) NVIC configuration if you need to use interrupt process (+++) Configure the SPIx interrupt priority (+++) Enable the NVIC SPI IRQ handle (##) DMA Configuration if you need to use DMA process (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_SPI_MspInit() API. [..] Circular mode restriction: (#) The DMA circular mode cannot be used when the SPI is configured in these modes: (##) Master 2Lines RxOnly (##) Master 1Line Rx (#) The CRC feature is not managed when the DMA circular mode is enabled (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ */ /** @defgroup SPI SPI * @brief SPI HAL module driver * @{ */ #ifdef HAL_SPI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define SPI_TIMEOUT_VALUE 10 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup SPI_Private_Functions * @{ */ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); static void SPI_TxISR(SPI_HandleTypeDef *hspi); static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); static void SPI_RxISR(SPI_HandleTypeDef *hspi); static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi); static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SPI_Exported_Functions SPI Exported Functions * @{ */ /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and de-initialize the SPIx peripheral: (+) User must implement HAL_SPI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). (+) Call the function HAL_SPI_Init() to configure the selected device with the selected configuration: (++) Mode (++) Direction (++) Data Size (++) Clock Polarity and Phase (++) NSS Management (++) BaudRate Prescaler (++) FirstBit (++) TIMode (++) CRC Calculation (++) CRC Polynomial if CRC enabled (+) Call the function HAL_SPI_DeInit() to restore the default configuration of the selected SPIx peripheral. @endverbatim * @{ */ /** * @brief Initializes the SPI according to the specified parameters * in the SPI_InitTypeDef and create the associated handle. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ if(hspi == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_SPI_MODE(hspi->Init.Mode)); assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); if(hspi->State == HAL_SPI_STATE_RESET) { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); } hspi->State = HAL_SPI_STATE_BUSY; /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); /* Configure : NSS management */ hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode); /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD); hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the SPI peripheral * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ if(hspi == NULL) { return HAL_ERROR; } /* Disable the SPI Peripheral Clock */ __HAL_SPI_DISABLE(hspi); /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_SPI_MspDeInit(hspi); hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hspi); return HAL_OK; } /** * @brief SPI MSP Init * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_MspInit could be implemented in the user file */ } /** * @brief SPI MSP DeInit * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SPI_MspDeInit could be implemented in the user file */ } /** * @} */ /** @defgroup SPI_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * @verbatim ============================================================================== ##### IO operation functions ##### =============================================================================== This subsection provides a set of functions allowing to manage the SPI data transfers. [..] The SPI supports master and slave mode : (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts or DMA, These APIs return the HAL status. The end of the data processing will be indicated through the dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks will be executed respectively at the end of the transmit or Receive process The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) exist for 1Line (simplex) and 2Lines (full duplex) modes. @endverbatim * @{ */ /** * @brief Transmit an amount of data in blocking mode * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { if(hspi->State == HAL_SPI_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); /* Configure communication */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; /*Init field not used in handle to zero */ hspi->TxISR = 0; hspi->RxISR = 0; hspi->RxXferSize = 0; hspi->RxXferCount = 0; /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { /* Configure communication direction : 1Line */ SPI_1LINE_TX(hspi); } /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Transmit data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) { hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } while(hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } } /* Transmit data in 16 Bit mode */ else { if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) { hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); hspi->pTxBuffPtr+=2; hspi->TxXferCount--; } while(hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); hspi->pTxBuffPtr+=2; hspi->TxXferCount--; } /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } } /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive an amount of data in blocking mode * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { __IO uint16_t tmpreg; uint32_t tmp = 0; if(hspi->State == HAL_SPI_STATE_READY) { if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hspi); /* Configure communication */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; /*Init field not used in handle to zero */ hspi->RxISR = 0; hspi->TxISR = 0; hspi->TxXferSize = 0; hspi->TxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { /* Process Unlocked */ __HAL_UNLOCK(hspi); /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Receive data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { while(hspi->RxXferCount > 1) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } (*hspi->pRxBuffPtr++) = hspi->Instance->DR; hspi->RxXferCount--; } /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } } /* Receive data in 16 Bit mode */ else { while(hspi->RxXferCount > 1) { /* Wait until RXNE flag is set to read data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; hspi->RxXferCount--; } /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } } /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } /* Receive last data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { (*hspi->pRxBuffPtr++) = hspi->Instance->DR; } /* Receive last data in 16 Bit mode */ else { *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; } hspi->RxXferCount--; /* Wait until RXNE flag is set: CRC Received */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_CRC; return HAL_TIMEOUT; } /* Read CRC to Flush RXNE flag */ tmpreg = hspi->Instance->DR; UNUSED(tmpreg); } if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); } hspi->State = HAL_SPI_STATE_READY; tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR); /* Check if CRC error occurred */ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET)) { hspi->ErrorCode |= HAL_SPI_ERROR_CRC; /* Reset CRC Calculation */ SPI_RESET_CRC(hspi); /* Process Unlocked */ __HAL_UNLOCK(hspi); return HAL_ERROR; } /* Process Unlocked */ __HAL_UNLOCK(hspi); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmit and Receive an amount of data in blocking mode * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer * @param pRxData: pointer to reception data buffer to be * @param Size: amount of data to be sent * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { __IO uint16_t tmpreg; uint32_t tmpstate = 0, tmp = 0; tmpstate = hspi->State; if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX)) { if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if(hspi->State == HAL_SPI_STATE_READY) { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; } /* Configure communication */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; hspi->pTxBuffPtr = pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; /*Init field not used in handle to zero */ hspi->RxISR = 0; hspi->TxISR = 0; /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Transmit and Receive data in 16 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) { if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) { hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); hspi->pTxBuffPtr+=2; hspi->TxXferCount--; } if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; hspi->RxXferCount--; } else { while(hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); hspi->pTxBuffPtr+=2; hspi->TxXferCount--; /* Enable CRC Transmission */ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; hspi->RxXferCount--; } /* Receive the last byte */ if(hspi->Init.Mode == SPI_MODE_SLAVE) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; hspi->RxXferCount--; } } } /* Transmit and Receive data in 8 Bit mode */ else { if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) { hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; } if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } (*hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->RxXferCount--; } else { while(hspi->TxXferCount > 0) { /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; /* Enable CRC Transmission */ if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; } /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } (*hspi->pRxBuffPtr++) = hspi->Instance->DR; hspi->RxXferCount--; } if(hspi->Init.Mode == SPI_MODE_SLAVE) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } (*hspi->pRxBuffPtr++) = hspi->Instance->DR; hspi->RxXferCount--; } } } /* Read CRC from DR to close CRC calculation process */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_CRC; return HAL_TIMEOUT; } /* Read CRC */ tmpreg = hspi->Instance->DR; UNUSED(tmpreg); } /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) { hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; return HAL_TIMEOUT; } hspi->State = HAL_SPI_STATE_READY; tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR); /* Check if CRC error occurred */ if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET)) { hspi->ErrorCode |= HAL_SPI_ERROR_CRC; /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } /* Process Unlocked */ __HAL_UNLOCK(hspi); return HAL_ERROR; } /* Process Unlocked */ __HAL_UNLOCK(hspi); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmit an amount of data in no-blocking mode with Interrupt * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { if(hspi->State == HAL_SPI_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); /* Configure communication */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->TxISR = &SPI_TxISR; hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; /*Init field not used in handle to zero */ hspi->RxISR = 0; hspi->RxXferSize = 0; hspi->RxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_TX(hspi); } /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { SPI_RESET_CRC(hspi); } if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); }else { /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); } /* Process Unlocked */ __HAL_UNLOCK(hspi); /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive an amount of data in no-blocking mode with Interrupt * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { if(hspi->State == HAL_SPI_STATE_READY) { if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hspi); /* Configure communication */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->RxISR = &SPI_RxISR; hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size ; /*Init field not used in handle to zero */ hspi->TxISR = 0; hspi->TxXferSize = 0; hspi->TxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { SPI_1LINE_RX(hspi); } else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode ==
/**
  ******************************************************************************
  * @file    stm32f4xx_hal_lptim.h
  * @author  MCD Application Team
  * @version V1.4.1
  * @date    09-October-2015
  * @brief   Header file of LPTIM HAL module.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */ 

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_LPTIM_H
#define __STM32F4xx_HAL_LPTIM_H

#ifdef __cplusplus
 extern "C" {
#endif

#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"

/** @addtogroup STM32F4xx_HAL_Driver
  * @{
  */

/** @defgroup LPTIM LPTIM
  * @brief LPTIM HAL module driver
  * @{
  */

/* Exported types ------------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
  * @{
  */

/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
  * @{
  */
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT  ((uint32_t)EXTI_IMR_MR23)  /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
/**
  * @}
  */
   
/** 
  * @brief  LPTIM Clock configuration definition  
  */
typedef struct
{
  uint32_t Source;         /*!< Selects the clock source.
                           This parameter can be a value of @ref LPTIM_Clock_Source   */

  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */

}LPTIM_ClockConfigTypeDef;

/** 
  * @brief  LPTIM Clock configuration definition  
  */
typedef struct
{
  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
                           if the ULPTIM input is selected.
                           Note: This parameter is used only when Ultra low power clock source is used.
                           Note: If the polarity is configured on 'both edges', an auxiliary clock
                           (one of the Low power oscillator) must be active.
                           This parameter can be a value of @ref LPTIM_Clock_Polarity */ 
  
  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
                           Note: This parameter is used only when Ultra low power clock source is used.
                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */  
  
}LPTIM_ULPClockConfigTypeDef;

/** 
  * @brief  LPTIM Trigger configuration definition  
  */
typedef struct
{
  uint32_t Source;        /*!< Selects the Trigger source.
                          This parameter can be a value of @ref LPTIM_Trigger_Source */
  
  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
                          Note: This parameter is used only when an external trigger is used.
                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
  
  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
                          Note: This parameter is used only when an external trigger is used.
                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */  
}LPTIM_TriggerConfigTypeDef;

/** 
  * @brief  LPTIM Initialization Structure definition  
  */
typedef struct
{                                                    
  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
                                                    
  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
                                                    
  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
                                                    
  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */
                                                    
  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autorelaod and the compare
                                                    values is done immediately or after the end of current period.
                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */

  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
                                                    or each external event.
                                                    This parameter can be a value of @ref LPTIM_Counter_Source */  
  
}LPTIM_InitTypeDef;

/** 
  * @brief  HAL LPTIM State structure definition  
  */ 
typedef enum __HAL_LPTIM_StateTypeDef
{
  HAL_LPTIM_STATE_RESET            = 0x00,    /*!< Peripheral not yet initialized or disabled  */
  HAL_LPTIM_STATE_READY            = 0x01,    /*!< Peripheral Initialized and ready for use    */
  HAL_LPTIM_STATE_BUSY             = 0x02,    /*!< An internal process is ongoing              */
  HAL_LPTIM_STATE_TIMEOUT          = 0x03,    /*!< Timeout state                               */
  HAL_LPTIM_STATE_ERROR            = 0x04     /*!< Internal Process is ongoing                 */
}HAL_LPTIM_StateTypeDef;

/** 
  * @brief  LPTIM handle Structure definition  
  */ 
typedef struct
{
      LPTIM_TypeDef              *Instance;         /*!< Register base address     */
      
      LPTIM_InitTypeDef           Init;             /*!< LPTIM required parameters */
  
      HAL_StatusTypeDef           Status;           /*!< LPTIM peripheral status   */
  
      HAL_LockTypeDef             Lock;             /*!< LPTIM locking object      */
  
   __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
  
}LPTIM_HandleTypeDef;

/**
  * @}
  */ 

/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
  * @{
  */

/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
  * @{
  */
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        ((uint32_t)0x00)
#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
/**
  * @}
  */

/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
  * @{
  */
#define LPTIM_PRESCALER_DIV1                    ((uint32_t)0x000000)
#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8                    ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
#define LPTIM_PRESCALER_DIV32                   ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define LPTIM_PRESCALER_DIV64                   ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define LPTIM_PRESCALER_DIV128                  ((uint32_t)LPTIM_CFGR_PRESC)
/**
  * @}
  */ 

/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
  * @{
  */

#define LPTIM_OUTPUTPOLARITY_HIGH               ((uint32_t)0x00000000)
#define LPTIM_OUTPUTPOLARITY_LOW                (LPTIM_CFGR_WAVPOL)
/**
  * @}
  */

/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
  * @{
  */
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS     LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS     LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS     LPTIM_CFGR_CKFLT
/**
  * @}
  */

/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
  * @{
  */

#define LPTIM_CLOCKPOLARITY_RISING                ((uint32_t)0x00000000)
#define LPTIM_CLOCKPOLARITY_FALLING               LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING        LPTIM_CFGR_CKPOL_1
/**
  * @}
  */

/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
  * @{
  */
#define LPTIM_TRIGSOURCE_SOFTWARE               ((uint32_t)0x0000FFFF)
#define LPTIM_TRIGSOURCE_0                      ((uint32_t)0x00000000)
#define LPTIM_TRIGSOURCE_1                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
#define LPTIM_TRIGSOURCE_5                      ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
/**
  * @}
  */

/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
  * @{
  */
#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
/**
  * @}
  */

/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
  * @{
  */
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  ((uint32_t)0x00000000)
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
/**
  * @}
  */

/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
  * @{
  */

#define LPTIM_UPDATE_IMMEDIATE                  ((uint32_t)0x00000000)
#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
/**
  * @}
  */

/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
  * @{
  */

#define LPTIM_COUNTERSOURCE_INTERNAL            ((uint32_t)0x00000000)
#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
/**
  * @}
  */
 
/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
  * @{
  */

#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
/**
  * @}
  */

/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
  * @{
  */

#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
#define LPTIM_IT_UP                              LPTIM_IER_UPIE
#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
/**
  * @}
  */
  
/** @defgroup LPTIM_Option Register Definition
  * @{
  */
#define LPTIM_OP_PAD_AF                          ((uint32_t)0x00000000)
#define LPTIM_OP_PAD_PA4                         LPTIM_OR_OR_0
#define LPTIM_OP_PAD_PB9                         LPTIM_OR_OR_1
#define LPTIM_OP_TIM_DAC                         LPTIM_OR_OR

/**
  * @}
  */

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
  * @{
  */

/** @brief Reset LPTIM handle state
  * @param  __HANDLE__: LPTIM handle
  * @retval None
  */
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)

/**
  * @brief  Enable/Disable the LPTIM peripheral.
  * @param  __HANDLE__: LPTIM handle
  * @retval None
  */
#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |=  (LPTIM_CR_ENABLE))
#define __HAL_LPTIM_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR &=  ~(LPTIM_CR_ENABLE))

/**
  * @brief  Starts the LPTIM peripheral in Continuous or in single mode.
  * @param  __HANDLE__: DMA handle
  * @retval None
  */
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
 
    
/**
  * @brief  Writes the passed parameter in the Autoreload register.
  * @param  __HANDLE__: LPTIM handle
  * @param  __VALUE__ : Autoreload value
  * @retval None
  */
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))

/**
  * @brief  Writes the passed parameter in the Compare register.
  * @param  __HANDLE__: LPTIM handle
  * @param  __VALUE__ : Compare value
  * @retval None
  */
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))

/**
  * @brief  Checks whether the specified LPTIM flag is set or not.
  * @param  __HANDLE__: LPTIM handle
  * @param  __FLAG__  : LPTIM flag to check
  *            This parameter can be a value of:
  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
  * @retval The state of the specified flag (SET or RESET).
  */
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

/**
  * @brief  Clears the specified LPTIM flag.
  * @param  __HANDLE__: LPTIM handle.
  * @param  __FLAG__  : LPTIM flag to clear.
  *            This parameter can be a value of:
  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
  * @retval None.
  */
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ICR  = (__FLAG__))

/**
  * @brief  Enable the specified LPTIM interrupt.
  * @param  __HANDLE__    : LPTIM handle.
  * @param  __INTERRUPT__ : LPTIM interrupt to set.
  *            This parameter can be a value of:
  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
  * @retval None.
  */
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))

 /**
  * @brief  Disable the specified LPTIM interrupt.
  * @param  __HANDLE__    : LPTIM handle.
  * @param  __INTERRUPT__ : LPTIM interrupt to set.
  *            This parameter can be a value of:
  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
  * @retval None.
  */
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))

    /**
  * @brief  Checks whether the specified LPTIM interrupt is set or not.
  * @param  __HANDLE__    : LPTIM handle.
  * @param  __INTERRUPT__ : LPTIM interrupt to check.
  *            This parameter can be a value of:
  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
  * @retval Interrupt status.
  */
    
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

/** @brief  LPTIM Option Register  
  * @param  __HANDLE__: LPTIM handle
  * @param   __VALUE__: This parameter can be a value of :
  *            @arg  LPTIM_OP_PAD_AF                        
  *            @arg  LPTIM_OP_PAD_PA4 
  *            @arg  LPTIM_OP_PAD_PB9                       
  *            @arg  LPTIM_OP_TIM_DAC  
  * @retval None
  */
#define __HAL_LPTIM_OPTR_CONFIG(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->OR  =  (__VALUE__))

/**
  * @brief  Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
  * @retval None
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @brief  Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
  * @retval None
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

/**
  * @brief  Enable event on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @brief  Disable event on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

/**
  * @brief  Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. 
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @brief  Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

/**
  * @brief  Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @brief  Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))

/**
  * @brief  Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();

/**
  * @brief  Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
  * This parameter can be:
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();

/**
  * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
  * @retval Line Status.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
  * @retval None.
  */
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)

/**
  * @}
  */   
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
  * @{
  */

/* Initialization/de-initialization functions  ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);

/* MSP functions  *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);

/* Start/Stop operation functions  *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);

/* ############################# One Pulse Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);

/* ############################## Set once Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);

/* ############################### Encoder Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);

/* ############################# Time out  Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);

/* ############################## Counter Mode ###############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);

/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);

/* LPTIM IRQ functions  *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);

/* CallBack functions  ********************************************************/
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);

/* Peripheral State functions  ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);

/**
  * @}
  */
  
/* Private types -------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Types LPTIM Private Types
  * @{
  */

/**
  * @}
  */ 

/* Private variables ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
  * @{
  */
  
/**
  * @}
  */ 

/* Private constants ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
  * @{
  */

/**
  * @}
  */ 

/* Private macros ------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
  * @{
  */

#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)           (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
                                                     ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__)     (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
                                                     ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)

#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)      (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
                                                     ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__)  (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
                                                     ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)       (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
                                                     ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

#define IS_LPTIM_TRG_SOURCE(__TRIG__)               (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
                                                     ((__TRIG__) == LPTIM_TRIGSOURCE_5))

#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__)        (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING         ) || \
                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
                                                     ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__)   (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
                                                     ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))		

#define IS_LPTIM_UPDATE_MODE(__MODE__)              (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
                                                     ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)         (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                     ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)         ((__AUTORELOAD__) <= 0x0000FFFF)

#define IS_LPTIM_COMPARE(__COMPARE__)               ((__COMPARE__) <= 0x0000FFFF)

#define IS_LPTIM_PERIOD(PERIOD)               ((PERIOD) <= 0x0000FFFF)

#define IS_LPTIM_PULSE(PULSE)                 ((PULSE) <= 0x0000FFFF)

/**
  * @}
  */ 

/* Private functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
  * @{
  */
  
/**
  * @}
  */
  
/**
  * @}
  */ 

/**
  * @}
  */

#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#ifdef __cplusplus
}
#endif

#endif /* __STM32F4xx_HAL_LPTIM_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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