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# Copyright (c) 2015-2016, NORDUnet A/S
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
# - Redistributions of source code must retain the above copyright notice,
#   this list of conditions and the following disclaimer.
#
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
#
# - Neither the name of the NORDUnet nor the names of its contributors may
#   be used to endorse or promote products derived from this software
#   without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

ifndef CRYPTECH_ROOT
  CRYPTECH_ROOT := $(abspath ../../..)
endif

LIBTFM_SRC	?= ${CRYPTECH_ROOT}/sw/thirdparty/libtfm
LIBTFM_BLD	?= ${LIBTFM_SRC}

LIBHAL_SRC	?= ${CRYPTECH_ROOT}/sw/libhal
LIBHAL_BLD	?= ${LIBHAL_SRC}

LIBS		= ${LIBHAL_BLD}/libhal.a ${LIBTFM_BLD}/libtfm.a

CFLAGS		?= -g3 -Wall -fPIC -std=c99 -I${LIBHAL_SRC} -I${LIBTFM_BLD}

BIN		= eim_peek_poke cores

all: $(if $(wildcard ${LIBHAL_BLD}/hal_io_eim.o),eim_peek_poke) $(if $(wildcard ${LIBHAL_BLD}/core.o),cores)

clean:
	rm -f *.o ${BIN}

${BIN}: %: %.o ${LIBS}
	${CC} ${CFLAGS} -o $@ $^ ${LDFLAGS}

%.o: %.c ${LIBHAL_SRC}/*.h
	${CC} ${CFLAGS} -c -o $@ $<
> 0] eim_da_out; reg eim_da_drive; reg eim_oe_n; reg eim_wr_n; wire eim_wait_n; assign eim_da = (eim_da_drive == 1'b1) ? eim_da_out : {16{1'bZ}}; // // UUT // novena_baseline_top uut ( .gclk_p_pin (gclk_p), .gclk_n_pin (gclk_n), .eim_bclk (eim_bclk), .eim_cs0_n (eim_cs_n), .eim_da (eim_da), .eim_lba_n (eim_lba_n), .eim_wr_n (eim_wr_n), .eim_oe_n (eim_oe_n), .eim_wait_n (eim_wait_n), .reset_mcu_b_pin (reset_mcu_b), .led_pin (led_pin), .apoptosis_pin (apoptosis_pin) ); // // CLK2 (50 MHz) // always #10 gclk = ~gclk; // // Initialize EIM // initial begin eim_cs_n = 1'b1; eim_bclk = 1'b0; eim_lba_n = 1'b1; eim_da_out = {16{1'bX}}; eim_da_drive = 1'b1; eim_oe_n = 1'b1; eim_wr_n = 1'b1; end // // Test Logic // reg [31: 0] eim_rd = {32{1'bX}}; initial begin gclk = 1'b0; reset_mcu_b = 1'b1; // #2000; // eim_write({12'h321, 2'd0, 2'b00}, 32'hAA_55_A5_A5); // write X #100; eim_write({12'h321, 2'd1, 2'b00}, 32'h11_22_12_12); // write Y #100; eim_read( {12'h321, 2'd3, 2'b00}, eim_rd); // read {STS, CTL} <-- should be 0x0000_0000 #100; eim_rd = eim_rd + 1'b1; eim_write({12'h321, 2'd3, 2'b00}, eim_rd); // write {STS, CTL} <-- STS is ignored by adder #100; eim_read( {12'h321, 2'd3, 2'b00}, eim_rd); // read {STS, CTL} <-- should be 0x0001_0001 #100; eim_read( {12'h321, 2'd2, 2'b00}, eim_rd); // read Z <-- should be 0xBB77B7B7 end // // Write Access // integer wr; task eim_write; input [15: 0] addr; input [31: 0] data; begin #15 eim_cs_n = 1'b0; eim_lba_n = 1'b0; eim_da_out = addr; eim_wr_n = 1'b0; #15 eim_bclk = 1'b1; #15 eim_bclk = 1'b0; eim_lba_n = 1'b1; eim_da_out = data[15:0]; #15 eim_bclk = 1'b1; #15 eim_bclk = 1'b0; eim_da_out = data[31:16]; #15 eim_bclk = 1'b1; #15 eim_bclk = 1'b0; eim_da_out = {16{1'bX}}; while (eim_wait_n == 1'b0) begin #15 eim_bclk = 1'b1; #15 eim_bclk = 1'b0; end #15 eim_cs_n = 1'b1; eim_wr_n = 1'b1; #30; end endtask; // // Read Access // task eim_read; input [15: 0] addr; output [31: 0] data; begin #15 eim_cs_n = 1'b0; eim_lba_n = 1'b0; eim_da_out = addr; #15 eim_bclk = 1'b1; #15 eim_bclk = 1'b0; eim_lba_n = 1'b1; eim_oe_n = 1'b0; eim_da_drive = 1'b0; #15; while (eim_wait_n == 1'b0) begin eim_bclk = 1'b1; #15 eim_bclk = 1'b0; #15; end eim_bclk = 1'b1; #15 eim_bclk = 1'b0; #15 eim_bclk = 1'b1; data[15: 0] = eim_da; #15 eim_bclk = 1'b0; #15 eim_bclk = 1'b1; data[31:16] = eim_da; #15 eim_bclk = 1'b0; eim_da_out = {16{1'bX}}; #15 eim_cs_n = 1'b1; eim_oe_n = 1'b1; eim_da_drive = 1'b1; #30; end endtask; endmodule