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/*
 * test-rpc_bighash.c
 * ------------------
 * Test code for RPC interface to Cryptech hash cores.
 *
 * Copyright (c) 2016, NORDUnet A/S
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 * - Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 *
 * - Neither the name of the NORDUnet nor the names of its contributors may
 *   be used to endorse or promote products derived from this software
 *   without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Throw a large hashing operation at the RPC server. This was originally
 * written to flush out an interaction between RPC and the CLI login
 * process (which uses PBKDF2, which uses HMAC-256). It might be useful
 * for other puposes?
 */

#include <stdio.h>
#include <string.h>

#include <hal.h>

static uint8_t block[] = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";

/* some common numbers of iterations, and their digests */
static uint8_t expected_5k[] = {
    0x28, 0xe6, 0x00, 0x2d, 0x7f, 0x18, 0x05, 0x42,
    0xdb, 0x89, 0xc9, 0x9f, 0xc1, 0x5f, 0x83, 0x16,
    0xe4, 0xc2, 0x15, 0x75, 0xad, 0xe5, 0x9f, 0xe7,
    0x22, 0x0a, 0x59, 0x72, 0x56, 0x28, 0x1f, 0xe8,
};

static uint8_t expected_10k[] = {
    0x2d, 0xb1, 0x9b, 0x83, 0x14, 0x86, 0x48, 0x18,
    0x76, 0x54, 0xec, 0xe0, 0xfc, 0x1a, 0x56, 0xfe,
    0xdc, 0xfa, 0x8f, 0x46, 0xfd, 0x9d, 0x88, 0x3a,
    0xcd, 0x59, 0x51, 0x92, 0x44, 0x89, 0xc8, 0x51,
};

static uint8_t expected_25k[] = {
    0xcb, 0xf2, 0x5c, 0x1d, 0x0a, 0xee, 0xfc, 0xf7,
    0xe7, 0x7f, 0xda, 0x9a, 0x81, 0x1f, 0x6c, 0xa9,
    0x80, 0x95, 0x04, 0x75, 0xdc, 0x3a, 0xc1, 0x18,
    0x68, 0x7b, 0xe7, 0x9e, 0xb4, 0x2e, 0x43, 0xe5,
};

static void hexdump(uint8_t *buf, uint32_t len)
{
    for (uint32_t i = 0; i < len; ++i)
        printf("%02x%c", buf[i], ((i & 0x07) == 0x07) ? '\n' : ' ');
    if ((len & 0x07) != 0)
        printf("\n");
}

#define check(op)                                               \
    do {                                                        \
        hal_error_t err = (op);                                 \
        if (err) {                                              \
            printf("%s: %s\n", #op, hal_error_string(err));     \
            return err;                                         \
        }                                                       \
    } while (0)

int main (int argc, char *argv[])
{
    hal_client_handle_t client = {0};
    hal_session_handle_t session = {0};
    hal_hash_handle_t hash;
    uint8_t digest[32];
    int iterations = 5000;
    uint8_t *expected;

    if (argc > 1)
        iterations = atoi(argv[1]);

    if (iterations == 5000)
        expected = expected_5k;
    else if (iterations == 10000)
        expected = expected_10k;
    else if (iterations == 25000)
        expected = expected_25k;
    else
        expected = NULL;

    check(hal_rpc_client_init());
    check(hal_rpc_hash_initialize(client, session, &hash, HAL_DIGEST_ALGORITHM_SHA256, NULL, 0));

    for (int i = 0; i < iterations; ++i) {
        check(hal_rpc_hash_update(hash, block, sizeof(block)));
    }

    check(hal_rpc_hash_finalize(hash, digest, sizeof(digest)));

    if (expected) {
        if (memcmp(digest, expected, sizeof(digest)) != 0) {
            printf("received:\n"); hexdump(digest, sizeof(digest));
            printf("\nexpected:\n"); hexdump(expected, sizeof(digest));
        }
    }
    else {
        hexdump(digest, sizeof(digest));
    }

    check(hal_rpc_client_close());
    return 0;
}
TEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /** * @} */ /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) /** * @} */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) /** * @} */ /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ #define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_DISABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) /** * @} */ /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) /** * @} */ /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) /** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} */ /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ #define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported Macros -----------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros * @{ */ /** @brief Configures the SysTick clock source. * @param __CLKSRC__: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__) \ do { \ if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK) \ { \ SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; \ } \ else \ SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; \ } while(0) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** * @} */ /** @addtogroup CORTEX_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ #if (__MPU_PRESENT == 1) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ ((GROUP) == NVIC_PRIORITYGROUP_1) || \ ((GROUP) == NVIC_PRIORITYGROUP_2) || \ ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) #if (__MPU_PRESENT == 1) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ ((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL2)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ ((TYPE) == MPU_REGION_FULL_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RO) || \ ((TYPE) == MPU_REGION_PRIV_RO_URO)) #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \ ((NUMBER) == MPU_REGION_NUMBER2) || \ ((NUMBER) == MPU_REGION_NUMBER3) || \ ((NUMBER) == MPU_REGION_NUMBER4) || \ ((NUMBER) == MPU_REGION_NUMBER5) || \ ((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER7)) #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \ ((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \ ((SIZE) == MPU_REGION_SIZE_2KB) || \ ((SIZE) == MPU_REGION_SIZE_4KB) || \ ((SIZE) == MPU_REGION_SIZE_8KB) || \ ((SIZE) == MPU_REGION_SIZE_16KB) || \ ((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB) || \ ((SIZE) == MPU_REGION_SIZE_256KB) || \ ((SIZE) == MPU_REGION_SIZE_512KB) || \ ((SIZE) == MPU_REGION_SIZE_1MB) || \ ((SIZE) == MPU_REGION_SIZE_2MB) || \ ((SIZE) == MPU_REGION_SIZE_4MB) || \ ((SIZE) == MPU_REGION_SIZE_8MB) || \ ((SIZE) == MPU_REGION_SIZE_16MB) || \ ((SIZE) == MPU_REGION_SIZE_32MB) || \ ((SIZE) == MPU_REGION_SIZE_64MB) || \ ((SIZE) == MPU_REGION_SIZE_128MB) || \ ((SIZE) == MPU_REGION_SIZE_256MB) || \ ((SIZE) == MPU_REGION_SIZE_512MB) || \ ((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CORTEX_Private_Functions CORTEX Private Functions * @brief CORTEX private functions * @{ */ #if (__MPU_PRESENT == 1) /** * @brief Disables the MPU * @retval None */ __STATIC_INLINE void HAL_MPU_Disable(void) { /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable the MPU */ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** * @brief Enables the MPU * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ __STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; } #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CORTEX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/