# The top level module should define the variables below then include # this file. The files listed should be in the same directory as the # Makefile. # # variable description # ---------- ------------- # project project name (top level module should match this name) # top_module top level module of the project # libdir path to library directory # libs library modules used # vfiles all local .v files # xilinx_cores all local .xco files # vendor vendor of FPGA (xilinx, altera, etc.) # family FPGA device family (spartan3e) # part FPGA part name (xc4vfx12-10-sf363) # flashsize size of flash for mcs file (16384) # optfile (optional) xst extra opttions file to put in .scr # map_opts (optional) options to give to map # par_opts (optional) options to give to par # intstyle (optional) intstyle option to all tools # ucf constraint file, defaults to $(project).ucf # # Library modules should have a modules.mk in their root directory, # namely $(libdir)//module.mk, that simply adds to the vfiles # and xilinx_cores variable. # # all the .xco files listed in xilinx_cores will be generated with core, with # the resulting .v and .ngc files placed back in the same directory as # the .xco file. # # TODO: .xco files are device dependant, should use a template based system coregen_work_dir ?= ./coregen-tmp #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt 2 -ir off -pr off -lc off -power off par_opts ?= -ol high -mt 4 isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh flashsize ?= 8192 ucf ?= $(project).ucf libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) mkfiles = $(libmks) xilinx.mk include $(libmks) corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc)) local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) junk += $(local_corengcs) .PHONY: default xilinx_cores clean twr etwr default: $(project).bit $(project).mcs xilinx_cores: $(corengcs) twr: $(project).twr etwr: $(project)_err.twr define cp_template $(2): $(1) cp $(1) $(2) endef $(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) %.ngc %.v: %.xco @echo "=== rebuilding $@" if [ -d $(coregen_work_dir) ]; then \ rm -rf $(coregen_work_dir)/*; \ else \ mkdir -p $(coregen_work_dir); \ fi cd $(coregen_work_dir); \ $(xil_env); \ coregen -b $$OLDPWD/$<; \ cd - xcodir=`dirname $<`; \ basename=`basename $< .xco`; \ if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \ echo "'$@' wasn't created."; \ exit 1; \ else \ cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \ fi junk += $(coregen_work_dir) date = $(shell date +%F-%H-%M) # some common junk junk += *.xrpt programming_files: $(project).bit $(project).mcs mkdir -p $@/$(date) mkdir -p $@/latest for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done $(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr $(project).mcs: $(project).bit $(xil_env); \ promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^ junk += $(project).mcs $(project).cfi $(project).prm $(project).bit: $(project)_par.ncd $(xil_env); \ bitgen $(intstyle) -g Compress -g UnusedPin:Pullnone -g Dri

test-aes-key-wrap