/*
 * novena-eim.h
 * ------------
 * This module contains the userland magic to set up and use the EIM bus.
 *
 *
 * Author: Pavel Shatov
 * Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 * - Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 *
 * - Neither the name of the NORDUnet nor the names of its contributors may
 *   be used to endorse or promote products derived from this software
 *   without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _NOVENA_EIM_H_
#define _NOVENA_EIM_H_

#include <stdint.h>
#include <sys/types.h>  /* Required for off_t, at least on Debian Wheezy. */

#define EIM_BASE_ADDR 0x08000000

/*
 * Set up EIM bus.
 * Returns 0 on success, -1 on failure.
 */

int  eim_setup(void);

/*
 * Write a 32-bit word to EIM.
 * If EIM is not set up correctly, this will abort with a bus error.
 */

void eim_write_32(off_t, uint32_t *);

/*
 * Read a 32-bit word from EIM.
 * If EIM is not set up correctly, this will abort with a bus error.
 */

void eim_read_32(off_t, uint32_t *);

#endif /* _NOVENA_EIM_H_ */

/*
 * Local variables:
 * indent-tabs-mode: nil
 * End:
 */
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<table class='blame blob'>
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<td class='hashes'><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-09-06 13:46:41 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-09-06 13:46:41 -0400

Add ECPoint I/O functions.  ASN.1 cleanup.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=12fd92723d71325b74a6c94eee4ca504773ad9da'>12fd927</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>


</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-09-06 13:46:41 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-09-06 13:46:41 -0400

Add ECPoint I/O functions.  ASN.1 cleanup.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=12fd92723d71325b74a6c94eee4ca504773ad9da'>12fd927</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-09-06 13:46:41 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-09-06 13:46:41 -0400

Add ECPoint I/O functions.  ASN.1 cleanup.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=12fd92723d71325b74a6c94eee4ca504773ad9da'>12fd927</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

































</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-21 23:08:51 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-21 23:08:51 -0400

libcryptech -&gt; libhal, doh.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=a3b7050c53a27d4cfeb350fb86e738f623e99e0c'>a3b7050</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 22:31:47 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 22:31:47 -0400

Whack libhal API to use current configure_core_selector mechanism.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=b3bbd3dbccef8c499e980490203cd5085dd13a98'>b3bbd3d</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>







</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>


</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>



</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>






</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>



</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>


</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>





</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>




</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>




</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>



</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>




</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>















</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
















</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400

off_t =&gt; hal_addr_t.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e164eecc55dd96efc98d2c723e96aaaecdcfda13'>e164eec</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400

off_t =&gt; hal_addr_t.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e164eecc55dd96efc98d2c723e96aaaecdcfda13'>e164eec</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>














</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>




</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400

off_t =&gt; hal_addr_t.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e164eecc55dd96efc98d2c723e96aaaecdcfda13'>e164eec</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>


</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 15:39:08 -0400

off_t =&gt; hal_addr_t.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e164eecc55dd96efc98d2c723e96aaaecdcfda13'>e164eec</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>


</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>


</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>



</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-20 16:57:33 -0400

Add csprng and hash modules.  Add real error codes instead of magic' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=fa13a8485ce07aecfbfa481baccfc33565f0be0d'>fa13a84</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>








</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>



</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>

</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-21 00:17:33 -0400

Copy Joachim&#x27;s EIM timeout change, make timeout configurable at' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=e2de6b1f6d220fc2481b19bd1ed203b493d2db18'>e2de6b1</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-10-04 23:23:07 -0400

Disallow NULL core argument in lowest-level HAL I/O routines.' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=ff4ff7c8ccf0c5d5c1c363053f0fc84ec5674edf'>ff4ff7c</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-05-19 23:49:18 -0400

Import FPGA I/O code from core/platform/novena/sw, add minimal' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=93941c6393ec3454c64528e537534284a81b04ac'>93941c6</a></span>
</pre></div><div class='alt'><pre><span class='sha1'><a title='author  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400
committer  Rob Austein &lt;sra@hactrn.net&gt;  2015-06-04 16:55:28 -0400

Disable HMAC-SHA-384 tests as neither my implementation nor PyCrypto' href='/sw/libhal/commit/hal_io_i2c.c?h=auto_magic&amp;id=cf865e9d768ab2dad37f82f071f0050b20f18506'>cf865e9</a></span>





</pre></div></td>
<td class='linenumbers'><div class='alt'><pre><a id='n1' href='#n1'>1</a>
</pre></div><div class='alt'><pre><a id='n2' href='#n2'>2</a>
<a id='n3' href='#n3'>3</a>
<a id='n4' href='#n4'>4</a>
</pre></div><div class='alt'><pre><a id='n5' href='#n5'>5</a>
</pre></div><div class='alt'><pre><a id='n6' href='#n6'>6</a>
<a id='n7' href='#n7'>7</a>
</pre></div><div class='alt'><pre><a id='n8' href='#n8'>8</a>
</pre></div><div class='alt'><pre><a id='n9' href='#n9'>9</a>
<a id='n10' href='#n10'>10</a>
<a id='n11' href='#n11'>11</a>
<a id='n12' href='#n12'>12</a>
<a id='n13' href='#n13'>13</a>
<a id='n14' href='#n14'>14</a>
<a id='n15' href='#n15'>15</a>
<a id='n16' href='#n16'>16</a>
<a id='n17' href='#n17'>17</a>
<a id='n18' href='#n18'>18</a>
<a id='n19' href='#n19'>19</a>
<a id='n20' href='#n20'>20</a>
<a id='n21' href='#n21'>21</a>
<a id='n22' href='#n22'>22</a>
<a id='n23' href='#n23'>23</a>
<a id='n24' href='#n24'>24</a>
<a id='n25' href='#n25'>25</a>
<a id='n26' href='#n26'>26</a>
<a id='n27' href='#n27'>27</a>
<a id='n28' href='#n28'>28</a>
<a id='n29' href='#n29'>29</a>
<a id='n30' href='#n30'>30</a>
<a id='n31' href='#n31'>31</a>
<a id='n32' href='#n32'>32</a>
<a id='n33' href='#n33'>33</a>
<a id='n34' href='#n34'>34</a>
<a id='n35' href='#n35'>35</a>
<a id='n36' href='#n36'>36</a>
<a id='n37' href='#n37'>37</a>
<a id='n38' href='#n38'>38</a>
<a id='n39' href='#n39'>39</a>
<a id='n40' href='#n40'>40</a>
<a id='n41' href='#n41'>41</a>
<a id='n42' href='#n42'>42</a>
</pre></div><div class='alt'><pre><a id='n43' href='#n43'>43</a>
</pre></div><div class='alt'><pre><a id='n44' href='#n44'>44</a>
</pre></div><div class='alt'><pre><a id='n45' href='#n45'>45</a>
<a id='n46' href='#n46'>46</a>
<a id='n47' href='#n47'>47</a>
<a id='n48' href='#n48'>48</a>
<a id='n49' href='#n49'>49</a>
<a id='n50' href='#n50'>50</a>
<a id='n51' href='#n51'>51</a>
<a id='n52' href='#n52'>52</a>
</pre></div><div class='alt'><pre><a id='n53' href='#n53'>53</a>
<a id='n54' href='#n54'>54</a>
<a id='n55' href='#n55'>55</a>
</pre></div><div class='alt'><pre><a id='n56' href='#n56'>56</a>
</pre></div><div class='alt'><pre><a id='n57' href='#n57'>57</a>
<a id='n58' href='#n58'>58</a>
<a id='n59' href='#n59'>59</a>
<a id='n60' href='#n60'>60</a>
</pre></div><div class='alt'><pre><a id='n61' href='#n61'>61</a>
<a id='n62' href='#n62'>62</a>
<a id='n63' href='#n63'>63</a>
<a id='n64' href='#n64'>64</a>
<a id='n65' href='#n65'>65</a>
<a id='n66' href='#n66'>66</a>
<a id='n67' href='#n67'>67</a>
</pre></div><div class='alt'><pre><a id='n68' href='#n68'>68</a>
<a id='n69' href='#n69'>69</a>
<a id='n70' href='#n70'>70</a>
<a id='n71' href='#n71'>71</a>
</pre></div><div class='alt'><pre><a id='n72' href='#n72'>72</a>
</pre></div><div class='alt'><pre><a id='n73' href='#n73'>73</a>
<a id='n74' href='#n74'>74</a>
</pre></div><div class='alt'><pre><a id='n75' href='#n75'>75</a>
</pre></div><div class='alt'><pre><a id='n76' href='#n76'>76</a>
</pre></div><div class='alt'><pre><a id='n77' href='#n77'>77</a>
</pre></div><div class='alt'><pre><a id='n78' href='#n78'>78</a>
</pre></div><div class='alt'><pre><a id='n79' href='#n79'>79</a>
<a id='n80' href='#n80'>80</a>
</pre></div><div class='alt'><pre><a id='n81' href='#n81'>81</a>
</pre></div><div class='alt'><pre><a id='n82' href='#n82'>82</a>
<a id='n83' href='#n83'>83</a>
<a id='n84' href='#n84'>84</a>
</pre></div><div class='alt'><pre><a id='n85' href='#n85'>85</a>
</pre></div><div class='alt'><pre><a id='n86' href='#n86'>86</a>
<a id='n87' href='#n87'>87</a>
<a id='n88' href='#n88'>88</a>
<a id='n89' href='#n89'>89</a>
<a id='n90' href='#n90'>90</a>
<a id='n91' href='#n91'>91</a>
</pre></div><div class='alt'><pre><a id='n92' href='#n92'>92</a>
</pre></div><div class='alt'><pre><a id='n93' href='#n93'>93</a>
<a id='n94' href='#n94'>94</a>
<a id='n95' href='#n95'>95</a>
<a id='n96' href='#n96'>96</a>
<a id='n97' href='#n97'>97</a>
</pre></div><div class='alt'><pre><a id='n98' href='#n98'>98</a>
</pre></div><div class='alt'><pre><a id='n99' href='#n99'>99</a>
<a id='n100' href='#n100'>100</a>
<a id='n101' href='#n101'>101</a>
<a id='n102' href='#n102'>102</a>
<a id='n103' href='#n103'>103</a>
</pre></div><div class='alt'><pre><a id='n104' href='#n104'>104</a>
</pre></div><div class='alt'><pre><a id='n105' href='#n105'>105</a>
<a id='n106' href='#n106'>106</a>
</pre></div><div class='alt'><pre><a id='n107' href='#n107'>107</a>
<a id='n108' href='#n108'>108</a>
</pre></div><div class='alt'><pre><a id='n109' href='#n109'>109</a>
<a id='n110' href='#n110'>110</a>
<a id='n111' href='#n111'>111</a>
<a id='n112' href='#n112'>112</a>
</pre></div><div class='alt'><pre><a id='n113' href='#n113'>113</a>
<a id='n114' href='#n114'>114</a>
</pre></div><div class='alt'><pre><a id='n115' href='#n115'>115</a>
</pre></div><div class='alt'><pre><a id='n116' href='#n116'>116</a>
</pre></div><div class='alt'><pre><a id='n117' href='#n117'>117</a>
</pre></div><div class='alt'><pre><a id='n118' href='#n118'>118</a>
</pre></div><div class='alt'><pre><a id='n119' href='#n119'>119</a>
<a id='n120' href='#n120'>120</a>
</pre></div><div class='alt'><pre><a id='n121' href='#n121'>121</a>
</pre></div><div class='alt'><pre><a id='n122' href='#n122'>122</a>
</pre></div><div class='alt'><pre><a id='n123' href='#n123'>123</a>
</pre></div><div class='alt'><pre><a id='n124' href='#n124'>124</a>
<a id='n125' href='#n125'>125</a>
<a id='n126' href='#n126'>126</a>
<a id='n127' href='#n127'>127</a>
<a id='n128' href='#n128'>128</a>
</pre></div><div class='alt'><pre><a id='n129' href='#n129'>129</a>
</pre></div><div class='alt'><pre><a id='n130' href='#n130'>130</a>
</pre></div><div class='alt'><pre><a id='n131' href='#n131'>131</a>
<a id='n132' href='#n132'>132</a>
</pre></div><div class='alt'><pre><a id='n133' href='#n133'>133</a>
</pre></div><div class='alt'><pre><a id='n134' href='#n134'>134</a>
</pre></div><div class='alt'><pre><a id='n135' href='#n135'>135</a>
<a id='n136' href='#n136'>136</a>
<a id='n137' href='#n137'>137</a>
<a id='n138' href='#n138'>138</a>
<a id='n139' href='#n139'>139</a>
<a id='n140' href='#n140'>140</a>
<a id='n141' href='#n141'>141</a>
<a id='n142' href='#n142'>142</a>
<a id='n143' href='#n143'>143</a>
<a id='n144' href='#n144'>144</a>
<a id='n145' href='#n145'>145</a>
<a id='n146' href='#n146'>146</a>
<a id='n147' href='#n147'>147</a>
<a id='n148' href='#n148'>148</a>
<a id='n149' href='#n149'>149</a>
<a id='n150' href='#n150'>150</a>
</pre></div><div class='alt'><pre><a id='n151' href='#n151'>151</a>
<a id='n152' href='#n152'>152</a>
</pre></div><div class='alt'><pre><a id='n153' href='#n153'>153</a>
<a id='n154' href='#n154'>154</a>
<a id='n155' href='#n155'>155</a>
<a id='n156' href='#n156'>156</a>
<a id='n157' href='#n157'>157</a>
<a id='n158' href='#n158'>158</a>
<a id='n159' href='#n159'>159</a>
<a id='n160' href='#n160'>160</a>
<a id='n161' href='#n161'>161</a>
<a id='n162' href='#n162'>162</a>
<a id='n163' href='#n163'>163</a>
<a id='n164' href='#n164'>164</a>
<a id='n165' href='#n165'>165</a>
<a id='n166' href='#n166'>166</a>
<a id='n167' href='#n167'>167</a>
<a id='n168' href='#n168'>168</a>
<a id='n169' href='#n169'>169</a>
</pre></div><div class='alt'><pre><a id='n170' href='#n170'>170</a>
</pre></div><div class='alt'><pre><a id='n171' href='#n171'>171</a>
</pre></div><div class='alt'><pre><a id='n172' href='#n172'>172</a>
</pre></div><div class='alt'><pre><a id='n173' href='#n173'>173</a>
</pre></div><div class='alt'><pre><a id='n174' href='#n174'>174</a>
</pre></div><div class='alt'><pre><a id='n175' href='#n175'>175</a>
<a id='n176' href='#n176'>176</a>
</pre></div><div class='alt'><pre><a id='n177' href='#n177'>177</a>
</pre></div><div class='alt'><pre><a id='n178' href='#n178'>178</a>
</pre></div><div class='alt'><pre><a id='n179' href='#n179'>179</a>
<a id='n180' href='#n180'>180</a>
</pre></div><div class='alt'><pre><a id='n181' href='#n181'>181</a>
<a id='n182' href='#n182'>182</a>
</pre></div><div class='alt'><pre><a id='n183' href='#n183'>183</a>
</pre></div><div class='alt'><pre><a id='n184' href='#n184'>184</a>
</pre></div><div class='alt'><pre><a id='n185' href='#n185'>185</a>
<a id='n186' href='#n186'>186</a>
<a id='n187' href='#n187'>187</a>
<a id='n188' href='#n188'>188</a>
<a id='n189' href='#n189'>189</a>
<a id='n190' href='#n190'>190</a>
<a id='n191' href='#n191'>191</a>
<a id='n192' href='#n192'>192</a>
<a id='n193' href='#n193'>193</a>
<a id='n194' href='#n194'>194</a>
<a id='n195' href='#n195'>195</a>
<a id='n196' href='#n196'>196</a>
<a id='n197' href='#n197'>197</a>
<a id='n198' href='#n198'>198</a>
<a id='n199' href='#n199'>199</a>
</pre></div><div class='alt'><pre><a id='n200' href='#n200'>200</a>
<a id='n201' href='#n201'>201</a>
</pre></div><div class='alt'><pre><a id='n202' href='#n202'>202</a>
</pre></div><div class='alt'><pre><a id='n203' href='#n203'>203</a>
<a id='n204' href='#n204'>204</a>
</pre></div><div class='alt'><pre><a id='n205' href='#n205'>205</a>
</pre></div><div class='alt'><pre><a id='n206' href='#n206'>206</a>
<a id='n207' href='#n207'>207</a>
</pre></div><div class='alt'><pre><a id='n208' href='#n208'>208</a>
<a id='n209' href='#n209'>209</a>
</pre></div><div class='alt'><pre><a id='n210' href='#n210'>210</a>
<a id='n211' href='#n211'>211</a>
</pre></div><div class='alt'><pre><a id='n212' href='#n212'>212</a>
</pre></div><div class='alt'><pre><a id='n213' href='#n213'>213</a>
<a id='n214' href='#n214'>214</a>
</pre></div><div class='alt'><pre><a id='n215' href='#n215'>215</a>
</pre></div><div class='alt'><pre><a id='n216' href='#n216'>216</a>
</pre></div><div class='alt'><pre><a id='n217' href='#n217'>217</a>
</pre></div><div class='alt'><pre><a id='n218' href='#n218'>218</a>
</pre></div><div class='alt'><pre><a id='n219' href='#n219'>219</a>
</pre></div><div class='alt'><pre><a id='n220' href='#n220'>220</a>
</pre></div><div class='alt'><pre><a id='n221' href='#n221'>221</a>
</pre></div><div class='alt'><pre><a id='n222' href='#n222'>222</a>
<a id='n223' href='#n223'>223</a>
</pre></div><div class='alt'><pre><a id='n224' href='#n224'>224</a>
</pre></div><div class='alt'><pre><a id='n225' href='#n225'>225</a>
</pre></div><div class='alt'><pre><a id='n226' href='#n226'>226</a>
</pre></div><div class='alt'><pre><a id='n227' href='#n227'>227</a>
</pre></div><div class='alt'><pre><a id='n228' href='#n228'>228</a>
<a id='n229' href='#n229'>229</a>
<a id='n230' href='#n230'>230</a>
<a id='n231' href='#n231'>231</a>
<a id='n232' href='#n232'>232</a>
</pre></div><div class='alt'><pre><a id='n233' href='#n233'>233</a>
</pre></div><div class='alt'><pre><a id='n234' href='#n234'>234</a>
</pre></div><div class='alt'><pre><a id='n235' href='#n235'>235</a>
<a id='n236' href='#n236'>236</a>
</pre></div><div class='alt'><pre><a id='n237' href='#n237'>237</a>
</pre></div><div class='alt'><pre><a id='n238' href='#n238'>238</a>
</pre></div><div class='alt'><pre><a id='n239' href='#n239'>239</a>
<a id='n240' href='#n240'>240</a>
<a id='n241' href='#n241'>241</a>
</pre></div><div class='alt'><pre><a id='n242' href='#n242'>242</a>
</pre></div><div class='alt'><pre><a id='n243' href='#n243'>243</a>
<a id='n244' href='#n244'>244</a>
</pre></div><div class='alt'><pre><a id='n245' href='#n245'>245</a>
</pre></div><div class='alt'><pre><a id='n246' href='#n246'>246</a>
</pre></div><div class='alt'><pre><a id='n247' href='#n247'>247</a>
<a id='n248' href='#n248'>248</a>
</pre></div><div class='alt'><pre><a id='n249' href='#n249'>249</a>
</pre></div><div class='alt'><pre><a id='n250' href='#n250'>250</a>
</pre></div><div class='alt'><pre><a id='n251' href='#n251'>251</a>
<a id='n252' href='#n252'>252</a>
<a id='n253' href='#n253'>253</a>
</pre></div><div class='alt'><pre><a id='n254' href='#n254'>254</a>
</pre></div><div class='alt'><pre><a id='n255' href='#n255'>255</a>
<a id='n256' href='#n256'>256</a>
<a id='n257' href='#n257'>257</a>
</pre></div><div class='alt'><pre><a id='n258' href='#n258'>258</a>
</pre></div><div class='alt'><pre><a id='n259' href='#n259'>259</a>
<a id='n260' href='#n260'>260</a>
</pre></div><div class='alt'><pre><a id='n261' href='#n261'>261</a>
</pre></div><div class='alt'><pre><a id='n262' href='#n262'>262</a>
<a id='n263' href='#n263'>263</a>
<a id='n264' href='#n264'>264</a>
<a id='n265' href='#n265'>265</a>
</pre></div><div class='alt'><pre><a id='n266' href='#n266'>266</a>
</pre></div><div class='alt'><pre><a id='n267' href='#n267'>267</a>
</pre></div><div class='alt'><pre><a id='n268' href='#n268'>268</a>
<a id='n269' href='#n269'>269</a>
</pre></div><div class='alt'><pre><a id='n270' href='#n270'>270</a>
</pre></div><div class='alt'><pre><a id='n271' href='#n271'>271</a>
</pre></div><div class='alt'><pre><a id='n272' href='#n272'>272</a>
</pre></div><div class='alt'><pre><a id='n273' href='#n273'>273</a>
</pre></div><div class='alt'><pre><a id='n274' href='#n274'>274</a>
<a id='n275' href='#n275'>275</a>
</pre></div><div class='alt'><pre><a id='n276' href='#n276'>276</a>
</pre></div><div class='alt'><pre><a id='n277' href='#n277'>277</a>
</pre></div><div class='alt'><pre><a id='n278' href='#n278'>278</a>
</pre></div><div class='alt'><pre><a id='n279' href='#n279'>279</a>
<a id='n280' href='#n280'>280</a>
</pre></div><div class='alt'><pre><a id='n281' href='#n281'>281</a>
</pre></div><div class='alt'><pre><a id='n282' href='#n282'>282</a>
</pre></div><div class='alt'><pre><a id='n283' href='#n283'>283</a>
</pre></div><div class='alt'><pre><a id='n284' href='#n284'>284</a>
</pre></div><div class='alt'><pre><a id='n285' href='#n285'>285</a>
<a id='n286' href='#n286'>286</a>
</pre></div><div class='alt'><pre><a id='n287' href='#n287'>287</a>
</pre></div><div class='alt'><pre><a id='n288' href='#n288'>288</a>
</pre></div><div class='alt'><pre><a id='n289' href='#n289'>289</a>
</pre></div><div class='alt'><pre><a id='n290' href='#n290'>290</a>
</pre></div><div class='alt'><pre><a id='n291' href='#n291'>291</a>
<a id='n292' href='#n292'>292</a>
</pre></div><div class='alt'><pre><a id='n293' href='#n293'>293</a>
</pre></div><div class='alt'><pre><a id='n294' href='#n294'>294</a>
</pre></div><div class='alt'><pre><a id='n295' href='#n295'>295</a>
</pre></div><div class='alt'><pre><a id='n296' href='#n296'>296</a>
</pre></div><div class='alt'><pre><a id='n297' href='#n297'>297</a>
<a id='n298' href='#n298'>298</a>
</pre></div><div class='alt'><pre><a id='n299' href='#n299'>299</a>
</pre></div><div class='alt'><pre><a id='n300' href='#n300'>300</a>
</pre></div><div class='alt'><pre><a id='n301' href='#n301'>301</a>
</pre></div><div class='alt'><pre><a id='n302' href='#n302'>302</a>
<a id='n303' href='#n303'>303</a>
</pre></div><div class='alt'><pre><a id='n304' href='#n304'>304</a>
</pre></div><div class='alt'><pre><a id='n305' href='#n305'>305</a>
</pre></div><div class='alt'><pre><a id='n306' href='#n306'>306</a>
</pre></div><div class='alt'><pre><a id='n307' href='#n307'>307</a>
</pre></div><div class='alt'><pre><a id='n308' href='#n308'>308</a>
<a id='n309' href='#n309'>309</a>
</pre></div><div class='alt'><pre><a id='n310' href='#n310'>310</a>
</pre></div><div class='alt'><pre><a id='n311' href='#n311'>311</a>
</pre></div><div class='alt'><pre><a id='n312' href='#n312'>312</a>
</pre></div><div class='alt'><pre><a id='n313' href='#n313'>313</a>
</pre></div><div class='alt'><pre><a id='n314' href='#n314'>314</a>
<a id='n315' href='#n315'>315</a>
</pre></div><div class='alt'><pre><a id='n316' href='#n316'>316</a>
</pre></div><div class='alt'><pre><a id='n317' href='#n317'>317</a>
</pre></div><div class='alt'><pre><a id='n318' href='#n318'>318</a>
<a id='n319' href='#n319'>319</a>
<a id='n320' href='#n320'>320</a>
<a id='n321' href='#n321'>321</a>
<a id='n322' href='#n322'>322</a>
<a id='n323' href='#n323'>323</a>
<a id='n324' href='#n324'>324</a>
<a id='n325' href='#n325'>325</a>
<a id='n326' href='#n326'>326</a>
</pre></div><div class='alt'><pre><a id='n327' href='#n327'>327</a>
</pre></div><div class='alt'><pre><a id='n328' href='#n328'>328</a>
<a id='n329' href='#n329'>329</a>
<a id='n330' href='#n330'>330</a>
<a id='n331' href='#n331'>331</a>
</pre></div><div class='alt'><pre><a id='n332' href='#n332'>332</a>
</pre></div><div class='alt'><pre><a id='n333' href='#n333'>333</a>
</pre></div><div class='alt'><pre><a id='n334' href='#n334'>334</a>
</pre></div><div class='alt'><pre><a id='n335' href='#n335'>335</a>
</pre></div><div class='alt'><pre><a id='n336' href='#n336'>336</a>
</pre></div><div class='alt'><pre><a id='n337' href='#n337'>337</a>
<a id='n338' href='#n338'>338</a>
</pre></div><div class='alt'><pre><a id='n339' href='#n339'>339</a>
</pre></div><div class='alt'><pre><a id='n340' href='#n340'>340</a>
</pre></div><div class='alt'><pre><a id='n341' href='#n341'>341</a>
</pre></div><div class='alt'><pre><a id='n342' href='#n342'>342</a>
</pre></div><div class='alt'><pre><a id='n343' href='#n343'>343</a>
<a id='n344' href='#n344'>344</a>
</pre></div><div class='alt'><pre><a id='n345' href='#n345'>345</a>
</pre></div><div class='alt'><pre><a id='n346' href='#n346'>346</a>
</pre></div><div class='alt'><pre><a id='n347' href='#n347'>347</a>
</pre></div><div class='alt'><pre><a id='n348' href='#n348'>348</a>
</pre></div><div class='alt'><pre><a id='n349' href='#n349'>349</a>
</pre></div><div class='alt'><pre><a id='n350' href='#n350'>350</a>
<a id='n351' href='#n351'>351</a>
<a id='n352' href='#n352'>352</a>
<a id='n353' href='#n353'>353</a>
<a id='n354' href='#n354'>354</a>
<a id='n355' href='#n355'>355</a>
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