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AgeCommit message (Expand)Author
2015-06-11First cut at RSA decryption/signature using the Chinese RemainderRob Austein
2015-06-10Operand lengths weren't including bug-workaround padding.Rob Austein
2015-06-10Add hal_modexp(), since the protocol is a bit complex. RewriteRob Austein
2015-06-05This time for sure, Rocky!Rob Austein
2015-06-05Get feedback cycle right in PBKDF2 iteration.Rob Austein
2015-06-05HMAC for truncated SHA-512 digests would probably work better if weRob Austein
2015-06-04First cut at PBKDF2.Rob Austein
2015-06-04Disable HMAC-SHA-384 tests as neither my implementation nor PyCryptoRob Austein
2015-06-04Whoops, we're supposed to hash an entire block for the key regardlessRob Austein
2015-06-04HMAC implementation and test vectors.Rob Austein
2015-06-04Refactor hash code prior to adding HMAC (which we need for PBKDF2).Rob Austein
2015-06-03ModExp now working!Rob Austein
2015-06-01Add padding options to test workaround for current ModExp bugs.Rob Austein
2015-05-28More fun with RSA test cases, still not working.Rob Austein
2015-05-27First pass at RSA tests.Rob Austein
2015-05-25Cleanup: names of *_core_present() functions, Makefile.Rob Austein
2015-05-25Doh, skip tests when we know core isn't present.Rob Austein
2015-05-25Add missing truncated SHA-512 cases.Rob Austein
2015-05-24Cleanup.Rob Austein
2015-05-24Debug hash-testing code.Rob Austein
2015-05-24First pass on hash test code.Rob Austein
2015-05-24AES key wrap now working with AES core.Rob Austein
2015-05-24Typing "!" when one meant "~" has interesting effects when bit masking.Rob Austein
2015-05-23Guess it might help to write the config value to the AES core afterRob Austein
2015-05-21Add test cases for 128-bit and 256-bit KEKs.Rob Austein
2015-05-21Add test harness: no useful tests yet, just the framework.Rob Austein
2015-05-21Copy Joachim's EIM timeout change, make timeout configurable atRob Austein
2015-05-20Add AES Key Wrap using Cryptech AES core.Rob Austein
2015-05-20Add csprng and hash modules. Add real error codes instead of magicRob Austein
2015-05-19Import FPGA I/O code from core/platform/novena/sw, add minimalRob Austein
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 16:23:49 +0000
------------------------------------------------------------- // // adder32_wrapper.v // ----------------------------------------------------------------------------- // Wrapper for 32-bit adder. // // Authors: Pavel Shatov // // Copyright (c) 2016, NORDUnet A/S // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // // - Neither the name of the NORDUnet nor the names of its contributors may be // used to endorse or promote products derived from this software without // specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // //------------------------------------------------------------------------------ module adder32_wrapper ( input clk, // clock input [31: 0] a, // operand input input [31: 0] b, // operand input output [31: 0] s, // sum output input c_in, // carry input output c_out // carry output ); // // Include Primitive Selector // `include "ecdsa_lowlevel_settings.v" // // Instantiate Vendor/Generic Primitive // `ADDER32_PRIMITIVE adder32_inst ( .clk(clk), .a(a), .b(b), .s(s), .c_in(c_in), .c_out(c_out) ); endmodule //------------------------------------------------------------------------------ // End-of-File //------------------------------------------------------------------------------