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| author | Rob Austein <sra@hactrn.net> | 2017-09-09 00:59:35 -0400 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2017-09-09 00:59:35 -0400 |
| commit | ca6432daebfcca16d55c07e588f96202d77109fb (patch) | |
| tree | e3282d9e622281e506b9e4090f7b7d7f8ba4efde /utils/load_novena_fpga | |
| parent | 63636301593c8a3952afae61c1b5f279c27f69ea (diff) | |
Start hacking for systolic modexp.
Work in progress. Probably won't even compile, much less run.
Requires corresponding new core/math/modexpa7 core.
No support (yet) for ASN.1 encoding of speedup factors or storage of
same in keystore.
No support (yet) for running CRT algorithm in parallel cores.
Minor cleanup of ancient bus I/O code, including EIM and I2C bus code
we'll probably never use again.
Diffstat (limited to 'utils/load_novena_fpga')
0 files changed, 0 insertions, 0 deletions