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authorRob Austein <sra@hactrn.net>2017-07-24 11:40:12 -0400
committerRob Austein <sra@hactrn.net>2017-07-24 11:40:12 -0400
commit19f92790c2f9fc7f4e019d7b20663453606f210f (patch)
treed787e42fcb1cf7ed6b06b7ea36bc910bbbb47416 /tests/time-keygen.py
parentc669159880c4b9564b8176c113e3c0778ca55851 (diff)
Split compile-time control of RSA ModExp.
At least for now, the speed tradeoff between software ModExp and our Verilog ModExp core differs significantly between signature and key generation. We don't really know why, but since key generation does not need to be constant time, we split out control over whether to use the software or FPGA implementation, so that we can use the FPGA for signature while using software for key generation. Revisit this if and when we figure out what the bottleneck is, as well as any time that the FPGA core itself changes significantly.
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