Split compile-time control of RSA ModExp.

At least for now, the speed tradeoff between software ModExp and our
Verilog ModExp core differs significantly between signature and key
generation.  We don't really know why, but since key generation does
not need to be constant time, we split out control over whether to use
the software or FPGA implementation, so that we can use the FPGA for
signature while using software for key generation.

Revisit this if and when we figure out what the bottleneck is, as well
as any time that the FPGA core itself changes significantly.

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