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# Copyright (c) 2015, NORDUnet A/S
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
# - Redistributions of source code must retain the above copyright notice,
#   this list of conditions and the following disclaimer.
#
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
#
# - Neither the name of the NORDUnet nor the names of its contributors may
#   be used to endorse or promote products derived from this software
#   without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

ifndef CRYPTECH_ROOT
  CRYPTECH_ROOT := $(abspath ../../..)
endif

LIBTFM_SRC	?= ${CRYPTECH_ROOT}/sw/thirdparty/libtfm
LIBTFM_BLD	?= ${LIBTFM_SRC}

LIBHAL_SRC	?= ${CRYPTECH_ROOT}/sw/libhal
LIBHAL_BLD	?= ${LIBHAL_SRC}

LIBS		= ${LIBHAL_BLD}/libhal.a ${LIBTFM_BLD}/libtfm.a

CFLAGS		?= -g3 -Wall -fPIC -std=c99 -I${LIBHAL_SRC} -I${LIBTFM_BLD}

# Which tests to build depends on how the library was compiled.

CORE_TESTS	= test-aes-key-wrap test-hash test-pbkdf2 test-ecdsa test-bus test-trng test-rsa test-mkmif
SERVER_TESTS	= test-rpc_server
CLIENT_TESTS	= test-rpc_hash test-rpc_pkey test-rpc_get_version test-rpc_get_random test-rpc_login test-rpc_bighash

ALL_TESTS	= ${CORE_TESTS} ${SERVER_TESTS} ${CLIENT_TESTS}

ifeq "${RPC_MODE}" "none"

  BIN += ${CORE_TESTS}

else ifeq "${RPC_MODE}" "server"

  BIN += ${CORE_TESTS} ${SERVER_TESTS}

else

  BIN += ${CLIENT_TESTS}

endif

$(info Building libhal with configuration IO_BUS=${IO_BUS} RPC_MODE=${RPC_MODE} KS=${KS} RPC_TRANSPORT=${RPC_TRANSPORT} MODEXP_CORE=${MODEXP_CORE})

all: ${BIN}

test: all
	for i in ${BIN}; do (set -x; ./$$i); done

clean distclean:
	rm -f *.o ${ALL_TESTS}

${BIN}: %: %.o ${LIBS}
	${CC} ${CFLAGS} -o $@ $^ ${LDFLAGS}

%.o: %.c ${LBHAL_SRC}/*.h ${LIBTFM_BLD}/tfm.h
	${CC} ${CFLAGS} -c -o $@ $<
ass="p">], key_reg[5], key_reg[6], key_reg[7]}; assign core_block = {block_reg[0], block_reg[1], block_reg[2], block_reg[3]}; assign core_init = init_reg; assign core_next = next_reg; assign core_encdec = encdec_reg; assign core_keylen = keylen_reg; //---------------------------------------------------------------- // core instantiation. //---------------------------------------------------------------- aes_core core( .clk(clk), .reset_n(reset_n), .encdec(core_encdec), .init(core_init), .next(core_next), .ready(core_ready), .key(core_key), .keylen(core_keylen), .block(core_block), .result(core_result), .result_valid(core_valid) ); //---------------------------------------------------------------- // reg_update // Update functionality for all registers in the core. // All registers are positive edge triggered with asynchronous // active low reset. //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin : reg_update integer i; if (!reset_n) begin for (i = 0 ; i < 4 ; i = i + 1) block_reg[i] <= 32'h0; for (i = 0 ; i < 8 ; i = i + 1) key_reg[i] <= 32'h0; init_reg <= 1'b0; next_reg <= 1'b0; encdec_reg <= 1'b0; keylen_reg <= 1'b0; end else begin init_reg <= init_new; next_reg <= next_new; if (config_we) begin encdec_reg <= write_data[CTRL_ENCDEC_BIT]; keylen_reg <= write_data[CTRL_KEYLEN_BIT]; end if (key_we) key_reg[address[2 : 0]] <= write_data; if (block_we) block_reg[address[1 : 0]] <= write_data; end end // reg_update //---------------------------------------------------------------- // api // // The interface command decoding logic. //---------------------------------------------------------------- always @* begin : api init_new = 1'b0; next_new = 1'b0; config_we = 1'b0; key_we = 1'b0; block_we = 1'b0; tmp_read_data = 32'h0; tmp_error = 1'b0; if (cs) begin if (we) begin if (address == ADDR_CTRL) begin init_new = write_data[CTRL_INIT_BIT]; next_new = write_data[CTRL_NEXT_BIT]; end if (address == ADDR_CONFIG) config_we = 1'b1; if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7)) key_we = 1'b1; if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3)) block_we = 1'b1; end // if (we) else begin case (address) ADDR_NAME0: tmp_read_data = CORE_NAME0; ADDR_NAME1: tmp_read_data = CORE_NAME1; ADDR_VERSION: tmp_read_data = CORE_VERSION; ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg}; ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready}; default: begin end endcase // case (address) if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3)) if (core_ready) tmp_read_data = core_result[(3 - (address - ADDR_RESULT0)) * 32 +: 32]; end end end // addr_decoder endmodule // aes //====================================================================== // EOF aes.v //======================================================================