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# Copyright (c) 2015, NORDUnet A/S
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
# - Redistributions of source code must retain the above copyright notice,
#   this list of conditions and the following disclaimer.
#
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
#
# - Neither the name of the NORDUnet nor the names of its contributors may
#   be used to endorse or promote products derived from this software
#   without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

ifndef CRYPTECH_ROOT
  CRYPTECH_ROOT := $(abspath ../../..)
endif

LIBTFM_SRC	?= ${CRYPTECH_ROOT}/sw/thirdparty/libtfm
LIBTFM_BLD	?= ${LIBTFM_SRC}

LIBHAL_SRC	?= ${CRYPTECH_ROOT}/sw/libhal
LIBHAL_BLD	?= ${LIBHAL_SRC}

LIBS		= ${LIBHAL_BLD}/libhal.a ${LIBTFM_BLD}/libtfm.a

CFLAGS		?= -g3 -Wall -fPIC -std=c99 -I${LIBHAL_SRC} -I${LIBTFM_BLD}

# Which tests to build depends on how the library was compiled.

CORE_TESTS	= test-aes-key-wrap test-hash test-pbkdf2 test-ecdsa test-bus test-trng test-rsa test-mkmif
SERVER_TESTS	= test-rpc_server
CLIENT_TESTS	= test-rpc_hash test-rpc_pkey test-rpc_get_version test-rpc_get_random test-rpc_login test-rpc_bighash

ALL_TESTS	= ${CORE_TESTS} ${SERVER_TESTS} ${CLIENT_TESTS}

ifeq "${RPC_MODE}" "none"

  BIN += ${CORE_TESTS}

else ifeq "${RPC_MODE}" "server"

  BIN += ${CORE_TESTS} ${SERVER_TESTS}

else

  BIN += ${CLIENT_TESTS}

endif

$(info Building libhal with configuration IO_BUS=${IO_BUS} RPC_MODE=${RPC_MODE} KS=${KS} RPC_TRANSPORT=${RPC_TRANSPORT} MODEXP_CORE=${MODEXP_CORE})

all: ${BIN}

test: all
	for i in ${BIN}; do (set -x; ./$$i); done

clean distclean:
	rm -f *.o ${ALL_TESTS}

${BIN}: %: %.o ${LIBS}
	${CC} ${CFLAGS} -o $@ $^ ${LDFLAGS}

%.o: %.c ${LBHAL_SRC}/*.h ${LIBTFM_BLD}/tfm.h
	${CC} ${CFLAGS} -c -o $@ $<
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 03:44:13 +0000
; parameter ADDR_KEY6 = 8'h16; parameter ADDR_KEY7 = 8'h17; parameter ADDR_BLOCK0 = 8'h20; parameter ADDR_BLOCK1 = 8'h21; parameter ADDR_BLOCK2 = 8'h22; parameter ADDR_BLOCK3 = 8'h23; parameter ADDR_RESULT0 = 8'h30; parameter ADDR_RESULT1 = 8'h31; parameter ADDR_RESULT2 = 8'h32; parameter ADDR_RESULT3 = 8'h33; parameter AES_128_BIT_KEY = 0; parameter AES_256_BIT_KEY = 1; parameter AES_DECIPHER = 1'b0; parameter AES_ENCIPHER = 1'b1; //---------------------------------------------------------------- // Register and Wire declarations. //---------------------------------------------------------------- reg [31 : 0] cycle_ctr; reg [31 : 0] error_ctr; reg [31 : 0] tc_ctr; reg [31 : 0] read_data; reg [127 : 0] result_data; reg tb_clk; reg tb_reset_n; reg tb_cs; reg tb_we; reg [7 : 0] tb_address; reg [31 : 0] tb_write_data; wire [31 : 0] tb_read_data; wire tb_error; //---------------------------------------------------------------- // Device Under Test. //---------------------------------------------------------------- aes dut( .clk(tb_clk), .reset_n(tb_reset_n), .cs(tb_cs), .we(tb_we), .address(tb_address), .write_data(tb_write_data), .read_data(tb_read_data), .error(tb_error) ); //---------------------------------------------------------------- // clk_gen // // Always running clock generator process. //---------------------------------------------------------------- always begin : clk_gen #CLK_HALF_PERIOD; tb_clk = !tb_clk; end // clk_gen //---------------------------------------------------------------- // sys_monitor() // // An always running process that creates a cycle counter and // conditionally displays information about the DUT. //---------------------------------------------------------------- always begin : sys_monitor cycle_ctr = cycle_ctr + 1; #(CLK_PERIOD); if (DEBUG) begin dump_dut_state(); end end //---------------------------------------------------------------- // dump_dut_state() // // Dump the state of the dump when needed. //---------------------------------------------------------------- task dump_dut_state; begin $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); $display("------------"); $display("ctrl_reg: init = 0x%01x, next = 0x%01x", dut.init_reg, dut.next_reg); $display("config_reg: encdec = 0x%01x, length = 0x%01x ", dut.encdec_reg, dut.keylen_reg); $display(""); $display("block: 0x%08x, 0x%08x, 0x%08x, 0x%08x", dut.block_reg[0], dut.block_reg[1], dut.block_reg[2], dut.block_reg[3]); $display(""); end endtask // dump_dut_state //---------------------------------------------------------------- // reset_dut() // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; #(2 * CLK_PERIOD); tb_reset_n = 1; $display(""); end endtask // reset_dut //---------------------------------------------------------------- // display_test_results() // // Display the accumulated test results. //---------------------------------------------------------------- task display_test_results; begin if (error_ctr == 0) begin $display("*** All %02d test cases completed successfully", tc_ctr); end else begin $display("*** %02d tests completed - %02d test cases did not complete successfully.", tc_ctr, error_ctr); end end endtask // display_test_results //---------------------------------------------------------------- // init_sim() // // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- task init_sim; begin cycle_ctr = 0; error_ctr = 0; tc_ctr = 0; tb_clk = 0; tb_reset_n = 1; tb_cs = 0; tb_we = 0; tb_address = 8'h0; tb_write_data = 32'h0; end endtask // init_sim //---------------------------------------------------------------- // write_word() // // Write the given word to the DUT using the DUT interface. //---------------------------------------------------------------- task write_word(input [11 : 0] address, input [31 : 0] word); begin if (DEBUG) begin $display("*** Writing 0x%08x to 0x%02x.", word, address); $display(""); end tb_address = address; tb_write_data = word; tb_cs = 1; tb_we = 1; #(2 * CLK_PERIOD); tb_cs = 0; tb_we = 0; end endtask // write_word //---------------------------------------------------------------- // write_block() // // Write the given block to the dut. //---------------------------------------------------------------- task write_block(input [127 : 0] block); begin write_word(ADDR_BLOCK0, block[127 : 96]); write_word(ADDR_BLOCK1, block[95 : 64]); write_word(ADDR_BLOCK2, block[63 : 32]); write_word(ADDR_BLOCK3, block[31 : 0]); end endtask // write_block //---------------------------------------------------------------- // read_word() // // Read a data word from the given address in the DUT. // the word read will be available in the global variable // read_data. //---------------------------------------------------------------- task read_word(input [11 : 0] address); begin tb_address = address; tb_cs = 1; tb_we = 0; #(CLK_PERIOD); read_data = tb_read_data; tb_cs = 0; if (DEBUG) begin $display("*** Reading 0x%08x from 0x%02x.", read_data, address); $display(""); end end endtask // read_word //---------------------------------------------------------------- // wait_ready // // Wait for the DUT to signal that the result is ready //---------------------------------------------------------------- task wait_ready; begin : wait_ready reg rdy; rdy = 0; while (rdy != 1) begin read_word(ADDR_STATUS); rdy = tb_read_data[0]; end end endtask // wait_ready //---------------------------------------------------------------- // read_result() // // Read the result block in the dut. //---------------------------------------------------------------- task read_result; begin read_word(ADDR_RESULT0); result_data[127 : 096] = read_data; read_word(ADDR_RESULT1); result_data[095 : 064] = read_data; read_word(ADDR_RESULT2); result_data[063 : 032] = read_data; read_word(ADDR_RESULT3); result_data[031 : 000] = read_data; end endtask // read_result //---------------------------------------------------------------- // init_key() // // init the key in the dut by writing the given key and // key length and then trigger init processing. //---------------------------------------------------------------- task init_key(input [255 : 0] key, input key_length); begin if (DEBUG) begin $display("key length: 0x%01x", key_length); $display("Initializing key expansion for key: 0x%016x", key); end write_word(ADDR_KEY0, key[255 : 224]); write_word(ADDR_KEY1, key[223 : 192]); write_word(ADDR_KEY2, key[191 : 160]); write_word(ADDR_KEY3, key[159 : 128]); write_word(ADDR_KEY4, key[127 : 96]); write_word(ADDR_KEY5, key[95 : 64]); write_word(ADDR_KEY6, key[63 : 32]); write_word(ADDR_KEY7, key[31 : 0]); if (key_length) begin write_word(ADDR_CONFIG, 8'h02); end else begin write_word(ADDR_CONFIG, 8'h00); end write_word(ADDR_CTRL, 8'h01); #(100 * CLK_PERIOD); end endtask // init_key //---------------------------------------------------------------- // ecb_mode_single_block_test() // // Perform ECB mode encryption or decryption single block test. //---------------------------------------------------------------- task ecb_mode_single_block_test(input [7 : 0] tc_number, input encdec, input [255 : 0] key, input key_length, input [127 : 0] block, input [127 : 0] expected); begin $display("*** TC %0d ECB mode test started.", tc_number); tc_ctr = tc_ctr + 1; init_key(key, key_length); write_block(block); dump_dut_state(); write_word(ADDR_CONFIG, (8'h00 + (key_length << 1)+ encdec)); write_word(ADDR_CTRL, 8'h02); wait_ready(); $display("*** Ready has been set!"); dump_dut_state(); read_result(); if (result_data == expected) begin $display("*** TC %0d successful.", tc_number); $display(""); end else begin $display("*** ERROR: TC %0d NOT successful.", tc_number); $display("Expected: 0x%032x", expected); $display("Got: 0x%032x", result_data); $display(""); error_ctr = error_ctr + 1; end end endtask // ecb_mode_single_block_test //---------------------------------------------------------------- // aes_test() // // Main test task will perform complete NIST test of AES. //---------------------------------------------------------------- task aes_test; reg [255 : 0] nist_aes128_key; reg [255 : 0] nist_aes256_key; reg [127 : 0] nist_plaintext0; reg [127 : 0] nist_plaintext1; reg [127 : 0] nist_plaintext2; reg [127 : 0] nist_plaintext3; reg [127 : 0] nist_ecb_128_enc_expected0; reg [127 : 0] nist_ecb_128_enc_expected1; reg [127 : 0] nist_ecb_128_enc_expected2; reg [127 : 0] nist_ecb_128_enc_expected3; reg [127 : 0] nist_ecb_256_enc_expected0; reg [127 : 0] nist_ecb_256_enc_expected1; reg [127 : 0] nist_ecb_256_enc_expected2; reg [127 : 0] nist_ecb_256_enc_expected3; begin nist_aes128_key = 256'h2b7e151628aed2a6abf7158809cf4f3c00000000000000000000000000000000; nist_aes256_key = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4; nist_plaintext0 = 128'h6bc1bee22e409f96e93d7e117393172a; nist_plaintext1 = 128'hae2d8a571e03ac9c9eb76fac45af8e51; nist_plaintext2 = 128'h30c81c46a35ce411e5fbc1191a0a52ef; nist_plaintext3 = 128'hf69f2445df4f9b17ad2b417be66c3710; nist_ecb_128_enc_expected0 = 128'h3ad77bb40d7a3660a89ecaf32466ef97; nist_ecb_128_enc_expected1 = 128'hf5d3d58503b9699de785895a96fdbaaf; nist_ecb_128_enc_expected2 = 128'h43b1cd7f598ece23881b00e3ed030688; nist_ecb_128_enc_expected3 = 128'h7b0c785e27e8ad3f8223207104725dd4; nist_ecb_256_enc_expected0 = 128'hf3eed1bdb5d2a03c064b5a7e3db181f8; nist_ecb_256_enc_expected1 = 128'h591ccb10d410ed26dc5ba74a31362870; nist_ecb_256_enc_expected2 = 128'hb6ed21b99ca6f4f9f153e7b1beafed1d; nist_ecb_256_enc_expected3 = 128'h23304b7a39f9f3ff067d8d8f9e24ecc7; $display("ECB 128 bit key tests"); $display("---------------------"); ecb_mode_single_block_test(8'h01, AES_ENCIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_plaintext0, nist_ecb_128_enc_expected0); ecb_mode_single_block_test(8'h02, AES_ENCIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_plaintext1, nist_ecb_128_enc_expected1); ecb_mode_single_block_test(8'h03, AES_ENCIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_plaintext2, nist_ecb_128_enc_expected2); ecb_mode_single_block_test(8'h04, AES_ENCIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_plaintext3, nist_ecb_128_enc_expected3); ecb_mode_single_block_test(8'h05, AES_DECIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_ecb_128_enc_expected0, nist_plaintext0); ecb_mode_single_block_test(8'h06, AES_DECIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_ecb_128_enc_expected1, nist_plaintext1); ecb_mode_single_block_test(8'h07, AES_DECIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_ecb_128_enc_expected2, nist_plaintext2); ecb_mode_single_block_test(8'h08, AES_DECIPHER, nist_aes128_key, AES_128_BIT_KEY, nist_ecb_128_enc_expected3, nist_plaintext3); $display(""); $display("ECB 256 bit key tests"); $display("---------------------"); ecb_mode_single_block_test(8'h10, AES_ENCIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_plaintext0, nist_ecb_256_enc_expected0); ecb_mode_single_block_test(8'h11, AES_ENCIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_plaintext1, nist_ecb_256_enc_expected1); ecb_mode_single_block_test(8'h12, AES_ENCIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_plaintext2, nist_ecb_256_enc_expected2); ecb_mode_single_block_test(8'h13, AES_ENCIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_plaintext3, nist_ecb_256_enc_expected3); ecb_mode_single_block_test(8'h14, AES_DECIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_ecb_256_enc_expected0, nist_plaintext0); ecb_mode_single_block_test(8'h15, AES_DECIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_ecb_256_enc_expected1, nist_plaintext1); ecb_mode_single_block_test(8'h16, AES_DECIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_ecb_256_enc_expected2, nist_plaintext2); ecb_mode_single_block_test(8'h17, AES_DECIPHER, nist_aes256_key, AES_256_BIT_KEY, nist_ecb_256_enc_expected3, nist_plaintext3); end endtask // aes_test //---------------------------------------------------------------- // main // // The main test functionality. //---------------------------------------------------------------- initial begin : main $display(" -= Testbench for AES started =-"); $display(" =============================="); $display(""); init_sim(); dump_dut_state(); reset_dut(); dump_dut_state(); aes_test(); display_test_results(); $display(""); $display("*** AES simulation done. ***"); $finish; end // main endmodule // tb_aes //====================================================================== // EOF tb_aes.v //======================================================================
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 03:44:13 +0000