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# Copyright (c) 2015, NORDUnet A/S
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
# - Redistributions of source code must retain the above copyright notice,
#   this list of conditions and the following disclaimer.
#
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
#
# - Neither the name of the NORDUnet nor the names of its contributors may
#   be used to endorse or promote products derived from this software
#   without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

ifndef CRYPTECH_ROOT
  CRYPTECH_ROOT := $(abspath ../../..)
endif

LIBTFM_SRC	?= ${CRYPTECH_ROOT}/sw/thirdparty/libtfm
LIBTFM_BLD	?= ${LIBTFM_SRC}

LIBHAL_SRC	?= ${CRYPTECH_ROOT}/sw/libhal
LIBHAL_BLD	?= ${LIBHAL_SRC}

LIBS		= ${LIBHAL_BLD}/libhal.a ${LIBTFM_BLD}/libtfm.a

CFLAGS		?= -g3 -Wall -fPIC -std=c99 -I${LIBHAL_SRC} -I${LIBTFM_BLD}

# Which tests to build depends on how the library was compiled.

CORE_TESTS	= test-aes-key-wrap test-hash test-pbkdf2 test-ecdsa test-bus test-trng test-rsa test-mkmif
SERVER_TESTS	= test-rpc_server
CLIENT_TESTS	= test-rpc_hash test-rpc_pkey test-rpc_get_version test-rpc_get_random test-rpc_login test-rpc_bighash test-xdr test-rpc_hashsig

ALL_TESTS	= ${CORE_TESTS} ${SERVER_TESTS} ${CLIENT_TESTS}

ifeq "${RPC_MODE}" "none"

  BIN += ${CORE_TESTS}

else ifeq "${RPC_MODE}" "server"

  BIN += ${CORE_TESTS} ${SERVER_TESTS}

else

  BIN += ${CLIENT_TESTS}

endif

$(info Building libhal with configuration IO_BUS=${IO_BUS} RPC_MODE=${RPC_MODE} KS=${KS} RPC_TRANSPORT=${RPC_TRANSPORT} MODEXP_CORE=${MODEXP_CORE})

all: ${BIN}

test: all
	for i in ${BIN}; do (set -x; ./$$i); done

clean distclean:
	rm -f *.o ${ALL_TESTS}

${BIN}: %: %.o ${LIBS}
	${CC} ${CFLAGS} -o $@ $^ ${LDFLAGS}

%.o: %.c ${LBHAL_SRC}/*.h ${LIBTFM_BLD}/tfm.h
	${CC} ${CFLAGS} -c -o $@ $<

test-rpc_hashsig.o: test-hashsig.h
quot; hidden="if_missing" type="Secondary_Report" file="netgen/translate/novena_baseline_top_translate.nlf" label="Post-Translate Simulation Model Report" > <toc-item title="Top of Report" target="Release" searchDir="Forward" /> </view> <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="novena_baseline_top_map.map" label="Map Log File" > <toc-item title="Top of Report" target="Release" searchDir="Forward" /> <toc-item title="Design Information" target="Design Information" /> <toc-item title="Design Summary" target="Design Summary" /> </view> <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_preroute.twr" label="Post-Map Static Timing Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> <toc-item title="Timing Report Description" target="Device,package,speed:" /> <toc-item title="Informational Messages" target="INFO:" /> <toc-item title="Warning Messages" target="WARNING:" /> <toc-item title="Timing Constraints" target="Timing constraint:" /> <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> <toc-item title="Data Sheet Report" target="Data Sheet report:" /> <toc-item title="Timing Summary" target="Timing summary:" /> <toc-item title="Trace Settings" target="Trace Settings:" /> </view> <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/novena_baseline_top_map.nlf" label="Post-Map Simulation Model Report" /> <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_map.psr" label="Physical Synthesis Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> </view> <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="novena_baseline_top_pad.txt" label="Pad Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> </view> <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="novena_baseline_top.unroutes" label="Unroutes Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> </view> <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_preroute.tsi" label="Post-Map Constraints Interaction Report" > <toc-item title="Top of Report" target="Release" searchDir="Forward" /> </view> <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.grf" label="Guide Results Report" /> <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.dly" label="Asynchronous Delay Report" /> <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.clk_rgn" label="Clock Region Report" /> <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.tsi" label="Post-Place and Route Constraints Interaction Report" > <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> </view> <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/novena_baseline_top_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top_sta.nlf" label="Primetime Netlist Report" > <toc-item title="Top of Report" target="Release" searchDir="Forward" /> </view> <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.ibs" label="IBIS Model" > <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> <toc-item title="Component" target="Component " /> </view> <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.lck" label="Back-annotate Pin Report" > <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> </view> <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="novena_baseline_top.lpc" label="Locked Pin Constraints" > <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> </view> <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/novena_baseline_top_timesim.nlf" label="Post-Fit Simulation Model Report" /> <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> </viewgroup> </body> </report-views>