From bdf3440027e4cd5a2bcf8d7a0b9bcab90eb9b765 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sat, 18 Apr 2020 17:30:15 -0400 Subject: Update submodules and add missing ones, as needed It's been a while since we did a full reproducible build via the releng tree. Some of the old modules are now obsolete, and a couple of the new ones weren't present. This is an initial test after updating the existing submodules and adding the missing ones. I don't really expect it to work, it's a first attempt. At minimum, we should go through and clean out submodules we no longer use, but that can wait until we figure out if we now have all the right modules and branches recorded here and whether the resulting configuration works properly. --- source/sw/stm32 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'source/sw/stm32') diff --git a/source/sw/stm32 b/source/sw/stm32 index e203f79..f09f1b8 160000 --- a/source/sw/stm32 +++ b/source/sw/stm32 @@ -1 +1 @@ -Subproject commit e203f797dddfcd03419e7ac336a86a6186fce0c1 +Subproject commit f09f1b8f4494e90ee672e92f3357229bdfb7d0ae -- cgit v1.2.3