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AgeCommit message (Collapse)Author
2018-08-23Faster ChaCha.Rob Austein
This fixes the last (currently) known problem for the 90MHz synchronous FMC bus clock. This time for sure!
2018-08-21Add explicit check for timing failure, per Pavel.Rob Austein
2018-08-18Pavel's fixes to Alpha synthesis.Rob Austein
2018-07-24Remove same TerASIC files on fmc_clk branch.Rob Austein
2018-07-14Adjust core/platform/alpha Makefile to track source changes.Rob Austein
2018-07-14First attempt at integrating Pavel's fmc_clk (synchronous FMC bus) code.Rob Austein
May not work out of the box, but committing this is the easiest way to let multiple people test the same build configuration.
2018-05-01Accumulated changes from last several months.Rob Austein
2017-12-15Try again with updated cores from Joachim.Rob Austein
2017-12-14Rewind most recent AES core changes.Rob Austein
Most recent AES core doesn't synthesize properly with core_selector, and we have other fixes to test. So back AES changes out of the releng build for now, re-add them when we sort this out.
2017-12-14Joachim's AES core updates.Rob Austein
2017-12-13Merge systolic_crt branches.Rob Austein
2017-12-12Pull recent bugfixes and cleanups. No new major functionality.Rob Austein
2017-05-12Enable ECDSA cores in default build.Rob Austein
2017-03-09Whoops, new build dependency on core/platform/common.Rob Austein
2017-03-07Drag in submodule changes.Rob Austein
2017-03-07Add ECDSA cores.Rob Austein
2016-12-28Pull in Joachim's updated ChaCha core.Rob Austein
2016-06-27First cut at consolidated alpha releng.Rob Austein
Undoubtedly doesn't work yet, and still needs doc, but perhaps now ready for testing on build machine.