index
:
releng/alpha
fmc_clk
master
Release engineering for Cryptech Alpha board
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
source
/
core
Age
Commit message (
Expand
)
Author
2020-01-01
Accumulated minor changes on fmc_clk branches
fmc_clk
Rob Austein
2019-01-22
Catch up with submodules
Rob Austein
2019-01-14
.vh search path and aes_speed un-fork.
Rob Austein
2019-01-08
Add Pavel's utility library.
Rob Austein
2019-01-08
Catch up with submodules
Rob Austein
2018-09-06
Incorporate recent timing/placement fixes.
Rob Austein
2018-08-27
xilinx.mk fixes.
Rob Austein
2018-08-23
Faster ChaCha.
Rob Austein
2018-08-21
Add explicit check for timing failure, per Pavel.
Rob Austein
2018-08-18
Pavel's fixes to Alpha synthesis.
Rob Austein
2018-07-24
Remove same TerASIC files on fmc_clk branch.
Rob Austein
2018-07-14
Adjust core/platform/alpha Makefile to track source changes.
Rob Austein
2018-07-14
First attempt at integrating Pavel's fmc_clk (synchronous FMC bus) code.
Rob Austein
2018-05-01
Accumulated changes from last several months.
Rob Austein
2017-12-15
Try again with updated cores from Joachim.
Rob Austein
2017-12-14
Rewind most recent AES core changes.
Rob Austein
2017-12-14
Joachim's AES core updates.
Rob Austein
2017-12-13
Merge systolic_crt branches.
Rob Austein
2017-12-12
Pull recent bugfixes and cleanups. No new major functionality.
Rob Austein
2017-05-12
Enable ECDSA cores in default build.
Rob Austein
2017-03-09
Whoops, new build dependency on core/platform/common.
Rob Austein
2017-03-07
Drag in submodule changes.
Rob Austein
2017-03-07
Add ECDSA cores.
Rob Austein
2016-12-28
Pull in Joachim's updated ChaCha core.
Rob Austein
2016-06-27
First cut at consolidated alpha releng.
Rob Austein
