releng/alpha - Release engineering for Cryptech Alpha board

Age	Commit message (Collapse)	Author
2020-04-18	Update submodules and add missing ones, as needed	Rob Austein
	It's been a while since we did a full reproducible build via the releng tree. Some of the old modules are now obsolete, and a couple of the new ones weren't present. This is an initial test after updating the existing submodules and adding the missing ones. I don't really expect it to work, it's a first attempt. At minimum, we should go through and clean out submodules we no longer use, but that can wait until we figure out if we now have all the right modules and branches recorded here and whether the resulting configuration works properly.
2019-04-09	Update for merge of fmc_clk_60mhz to master and hardware byteswapping.	Paul Selkirk
	This also catches some recent-ish changes to aes, chacha, and rosc_entropy.
2019-01-22	Catch up with submodules	Rob Austein

2019-01-14	.vh search path and aes_speed un-fork.	Rob Austein

2019-01-08	Catch up with submodules	Rob Austein

2017-12-13	Merge systolic_crt branches.	Rob Austein

2017-12-12	Pull recent bugfixes and cleanups. No new major functionality.	Rob Austein

2017-05-12	Enable ECDSA cores in default build.	Rob Austein

2017-03-09	Whoops, new build dependency on core/platform/common.	Rob Austein

2017-03-07	Drag in submodule changes.	Rob Austein

2016-06-27	First cut at consolidated alpha releng.	Rob Austein
	Undoubtedly doesn't work yet, and still needs doc, but perhaps now ready for testing on build machine.