| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-06-28 | Tweak build-shadow-tree.py to adjust an existing tree as well as creating a ↵ | Rob Austein | |
| new one. Original design intent was that the build tree be created once then left alone, but this turns out to be short-sighted: we really don't want to have to re-synthesize all of the Verilog code just because somebody added a new C file to the firmware. | |||
| 2016-06-27 | Mostly working. A few scripts still missing from binary packages, and no ↵ | Rob Austein | |
| Homebrew yet. | |||
| 2016-06-27 | First cut at consolidated alpha releng. | Rob Austein | |
| Undoubtedly doesn't work yet, and still needs doc, but perhaps now ready for testing on build machine. | |||
 |
index : releng/alpha | |
| Release engineering for Cryptech Alpha board | git repositories |
| aboutsummaryrefslogtreecommitdiff |
path: root/build-shadow-tree.py