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Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 21 |
1 files changed, 10 insertions, 11 deletions
@@ -6,21 +6,21 @@ serial SRAM with a SPI interface. ## Purpose and Functionality ## -The Master Key Memory is where a cryptographic master key is stored. the +The Master Key Memory is where a cryptographic master key is stored. The key is used (for example) to cryptographically wrap other keys and secrets. By wiping the MKM and thus the master key, the wrapped secrets are protected against leakage to a local attacker that physically breaks -an actuve tamper detect shield. +an active tamper detect shield. -The core will in future versions provide functionality to autonomosly -protect against memory remanence effects by rotating bits in stored data +The core will in future versions provide functionality to autonomously +protect against memory remanence effects by rotating bits in stored data, and moving data to different addresses in the external memory. The core -will also be able to automously zeroise the memory when given an alarm +will also be able to autonomously zeroise the memory when given an alarm signal. The current version however simply provides an interface to the slower, serial memory including initializing the memory in the correct mode. The -core supports three commands: read word, write word and initalize +core supports three commands: read word, write word, and initialize memory. @@ -29,7 +29,7 @@ The SPI clock is generated by the core clock (clk) divided by the SPI clock divisor * 2 (the divisor is the half period in cycles). The default divisor is set to generate an SPI clock of less than 1 MHz when the core clock is 50 MHz. For other speeds and other -core frequencies the divisor will have to be adjusted. +core frequencies, the divisor will have to be adjusted. The core will only read and write complete 32-bit words. @@ -45,12 +45,11 @@ The implementation is divided into three parts: read data. The SPI interface also generates the SPI clock and chip enable. -- A command handler core that tha read and write words as well as send +- A Microchip-specific command handler that sends the read, write, and init commands to the memory using the SPI interface. - An API interface that provides the ability to configure the SPI clock - speed, setting the address to be read or written and data access. - + speed, set the address to read or write, and data access. The current implementation will initiate the Microchip memory directly after reset and set the memory in sequential mode. This means that it @@ -94,7 +93,7 @@ to remove the need to update the address between bytes. **(2016-05-10)** The core has now been verified in a Xilinx Spartan-6 FPGA and the target -Microchip memory connected to the FPGA.memory. Read and write access has +Microchip memory connected to the FPGA memory. Read and write access has successfully been performed with SPI clock speeds from 300 Hz to 10 MHz. |