From 9e08b2d3f5cdcca969f13c2cacd4511693848d59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 28 Jun 2018 16:04:13 +0200 Subject: Adding a lot of functionality. Starting to get everthing in place. --- src/rtl/keywrap_mem.v | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) (limited to 'src/rtl/keywrap_mem.v') diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v index dc1d873..d31c76c 100644 --- a/src/rtl/keywrap_mem.v +++ b/src/rtl/keywrap_mem.v @@ -69,19 +69,19 @@ module keywrap_mem ( //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - reg [31 : 0] tmp_api_rd_data0; - reg [31 : 0] tmp_api_rd_data1; - reg [31 : 0] muxed_tmp_api_rd_data; + reg [31 : 0] api_rd_data0; + reg [31 : 0] api_rd_data1; + reg [31 : 0] muxed_api_rd_data; - reg [31 : 0] tmp_core_rd_data0; - reg [31 : 0] tmp_core_rd_data1; + reg [31 : 0] core_rd_data0; + reg [31 : 0] core_rd_data1; //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- - assign api_rd_data = muxed_tmp_api_rd_data; - assign core_rd_data = {tmp_core_rd_data1, tmp_core_rd_data0}; + assign api_rd_data = muxed_api_rd_data; + assign core_rd_data = {core_rd_data1, core_rd_data0}; //---------------------------------------------------------------- @@ -89,8 +89,8 @@ module keywrap_mem ( //---------------------------------------------------------------- always @(posedge clk) begin : mem0_access - tmp_core_rd_data0 <= mem0[core_addr]; - tmp_api_rd_data0 <= mem0[api_addr[13 : 1]]; + core_rd_data0 <= mem0[core_addr]; + api_rd_data0 <= mem0[api_addr[13 : 1]]; if (mem0_we) mem0[mem0_addr] <= mem0_data; @@ -102,8 +102,8 @@ module keywrap_mem ( //---------------------------------------------------------------- always @(posedge clk) begin : mem1_access - tmp_core_rd_data1 <= mem1[core_addr]; - tmp_api_rd_data1 <= mem1[api_addr[13 : 1]]; + core_rd_data1 <= mem1[core_addr]; + api_rd_data1 <= mem1[api_addr[13 : 1]]; if (mem1_we) mem1[mem1_addr] <= mem1_data; @@ -111,13 +111,14 @@ module keywrap_mem ( //---------------------------------------------------------------- + // api_rd_data_mux //---------------------------------------------------------------- always @* - begin + begin : api_rd_data_mux if (api_addr[0]) - muxed_tmp_api_rd_data = tmp_api_rd_data1; + muxed_api_rd_data = api_rd_data1; else - muxed_tmp_api_rd_data = tmp_api_rd_data0; + muxed_api_rd_data = api_rd_data0; end -- cgit v1.2.3