From 36fcc28a75ed9fa6d0dc76d9ff3351ee1dd63b89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 22 Jun 2018 08:32:33 +0200 Subject: (1) Added initial version of keywrap_core which will implement the actual wrapping using aes_core and the keywrap_mem. (2) Minor cleanup to the keywrap_mem code. --- src/rtl/keywrap_mem.v | 50 ++++++++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 24 deletions(-) (limited to 'src/rtl/keywrap_mem.v') diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v index 8ddb465..e54798a 100644 --- a/src/rtl/keywrap_mem.v +++ b/src/rtl/keywrap_mem.v @@ -37,45 +37,47 @@ // //====================================================================== -module keywrap_mem +module keywrap_mem ( + input wire clk, + input wire reset_n, - ( - input wire clk, - input wire reset_n, + input wire api_we, + input wire [13 : 0] api_addr, + input wire [31 : 0] api_wr_data, + output wire [31 : 0] api_rd_data, - input wire api_we, - input wire [13 : 0] api_addr, - input wire [31 : 0] api_wr_data, - output wire [31 : 0] api_rd_data, - - input wire core_we, - input wire [12 : 0] core_addr, - input wire [63 : 0] core_wr_data, - output wire [63 : 0] core_rd_data - ); + input wire core_we, + input wire [12 : 0] core_addr, + input wire [63 : 0] core_wr_data, + output wire [63 : 0] core_rd_data + ); //---------------------------------------------------------------- - // Registers and memories including conntrol signals. + // Registers and memories including control signals. //---------------------------------------------------------------- - reg [31 : 0] tmp_api_rd_data0; - reg [31 : 0] tmp_api_rd_data1; - reg [31 : 0] muxed_tmp_api_rd_data; - - reg [31 : 0] tmp_core_rd_data0; - reg [31 : 0] tmp_core_rd_data1; - reg [31 : 0] mem0 [0 : 8191]; reg [31 : 0] mem0_data; - reg [12 : 0] mem0_addr; + reg [12 : 0] mem0_addr; reg mem0_we; reg [31 : 0] mem1 [0 : 8191]; reg [31 : 0] mem1_data; - reg [12 : 0] mem1_addr; + reg [12 : 0] mem1_addr; reg mem1_we; + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + reg [31 : 0] tmp_api_rd_data0; + reg [31 : 0] tmp_api_rd_data1; + reg [31 : 0] muxed_tmp_api_rd_data; + + reg [31 : 0] tmp_core_rd_data0; + reg [31 : 0] tmp_core_rd_data1; + + //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- -- cgit v1.2.3