From 311ab5f3d9b9c6777e8d4377c6774f2c47cb577f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Thu, 28 Jun 2018 14:35:04 +0200
Subject: A lot of cleanup of interconnections between cores and hierarchy.
 Fixed a number of nits and bugs. Added address generator for the API.

---
 src/rtl/keywrap.v      |  2 +-
 src/rtl/keywrap_core.v | 53 +++++++++++++++++++++++++++++++++++++++-----------
 src/rtl/keywrap_mem.v  |  5 ++---
 3 files changed, 45 insertions(+), 15 deletions(-)

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 9b80008..b656299 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -107,7 +107,7 @@ module keywrap(
   reg api_we_new;
 
   reg [12 : 0] rlen_reg;
-  reg [12 : 0] rlen_we;
+  reg          rlen_we;
 
   reg [31 : 0] key_reg [0 : 7];
   reg          key_we;
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 8d0e455..6e29d45 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -88,6 +88,12 @@ module keywrap_core (
   reg          ready_new;
   reg          ready_we;
 
+  reg [13 : 0] api_addr_ctr_reg;
+  reg [13 : 0] api_addr_ctr_new;
+  reg          api_addr_ctr_we;
+  reg          api_addr_ctr_inc;
+  reg          api_addr_ctr_rst;
+
   reg [12 : 0] block_ctr_reg;
   reg [12 : 0] block_ctr_new;
   reg          block_ctr_we;
@@ -114,8 +120,6 @@ module keywrap_core (
   reg            aes_init;
   reg            aes_next;
   wire           aes_ready;
-  wire [255 : 0] aes_key;
-  wire           aes_keylen;
   reg  [127 : 0] aes_block;
   wire [127 : 0] aes_result;
   wire           aes_valid;
@@ -131,28 +135,33 @@ module keywrap_core (
   //----------------------------------------------------------------
   keywrap_mem mem(
                   .clk(clk),
-                  .reset_n(reset_n),
+
                   .api_we(api_we),
-                  .api_addr(api_addr),
+                  .api_addr(api_addr_ctr_reg),
                   .api_wr_data(api_wr_data),
                   .api_rd_data(api_rd_data),
-                  .core_we(),
-                  .core_addr(),
-                  .core_wr_data(),
-                  .core_rd_data()
+
+                  .core_we(core_we),
+                  .core_addr(core_addr),
+                  .core_wr_data(core_wr_data),
+                  .core_rd_data(core_rd_data)
                  );
 
 
   aes_core aes(
                .clk(clk),
                .reset_n(reset_n),
+
                .encdec(aes_encdec),
                .init(aes_init),
                .next(aes_next),
-               .ready(aes_ready),
-               .key(aes_key),
-               .keylen(aes_keylen),
+
+               .key(key),
+               .keylen(keylen),
+
                .block(aes_block),
+
+               .ready(aes_ready),
                .result(aes_result),
                .result_valid(aes_valid)
               );
@@ -182,6 +191,28 @@ module keywrap_core (
     end // reg_update
 
 
+  //----------------------------------------------------------------
+  // api_addr_ctr
+  //----------------------------------------------------------------
+  always @*
+    begin : api_addr_ctr
+      api_addr_ctr_new = 14'h0;
+      api_addr_ctr_we  = 1'h0;
+
+      if (api_addr_ctr_rst)
+        begin
+          api_addr_ctr_new = 14'h0;
+          api_addr_ctr_we  = 1'h1;
+        end
+
+      if (api_addr_ctr_inc)
+        begin
+          api_addr_ctr_new = api_addr_ctr_reg + 1'h1;
+          api_addr_ctr_we  = 1'h1;
+        end
+    end
+
+
   //----------------------------------------------------------------
   // block_ctr
   //----------------------------------------------------------------
diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index e54798a..dc1d873 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -39,7 +39,6 @@
 
 module keywrap_mem (
                     input wire           clk,
-                    input wire           reset_n,
 
                     input wire           api_we,
                     input wire [13 : 0]  api_addr,
@@ -130,10 +129,10 @@ module keywrap_mem (
   always @*
     begin : write_mux
       mem0_data = 32'h0;
-      mem0_addr = 8'h0;
+      mem0_addr = 13'h0;
       mem0_we   = 1'h0;
       mem1_data = 32'h0;
-      mem1_addr = 8'h0;
+      mem1_addr = 13'h0;
       mem1_we   = 1'h0;
 
       if (core_we)
-- 
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