From f20979faa37d4f272fcce51af18b829027778614 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 14 Sep 2018 16:07:25 +0200 Subject: Adding instatiation of the mkmif in the keywrap top level wrapper. Updated testbench anf Makefile to build with instantiated mkmif. The mkmif is not yet used by the keywrap. --- src/rtl/keywrap.v | 43 ++++++++++++++++++++++++++++++++++++++++++- src/tb/tb_keywrap.v | 24 +++++++++++++++++------- toolruns/Makefile | 5 ++++- 3 files changed, 63 insertions(+), 9 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index f8fcbd7..b394c9c 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -53,6 +53,11 @@ module keywrap #(parameter ADDR_BITS = 13) input wire clk, input wire reset_n, + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + input wire cs, input wire we, @@ -150,6 +155,12 @@ module keywrap #(parameter ADDR_BITS = 13) wire [63 : 0] core_a_result; wire [31 : 0] core_api_rd_data; + reg mem_cs; + reg mem_we; + reg [7 : 0] mem_address; + reg [31 : 0] mem_write_data; + wire [31 : 0] mem_read_data; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -166,7 +177,7 @@ module keywrap #(parameter ADDR_BITS = 13) //---------------------------------------------------------------- - // core instantiation. + // keywrap core instantiation. //---------------------------------------------------------------- keywrap_core #(.MEM_BITS(MEM_BITS)) core( @@ -194,6 +205,22 @@ module keywrap #(parameter ADDR_BITS = 13) .api_rd_data(core_api_rd_data) ); + mkmif memory( + .clk(clk), + .reset_n(reset_n), + + .spi_sclk(mkm_spi_sclk), + .spi_cs_n(mkm_spi_cs_n), + .spi_do(mkm_spi_do), + .spi_di(mkm_spi_di), + + .cs(mem_cs), + .we(mem_we), + .address(mem_address), + .write_data(mem_write_data), + .read_data(mem_read_data) + ); + //---------------------------------------------------------------- // reg_update @@ -330,6 +357,20 @@ module keywrap #(parameter ADDR_BITS = 13) end // else: !if(we) end // if (cs) end // block: api + + + //---------------------------------------------------------------- + // mkmif_ctrl + // Logic needed to handle the integratrion of the mkmif + //---------------------------------------------------------------- + always @* + begin : mkmif_ctrl + mem_cs = 1'h0; + mem_we = 1'h0; + mem_address = 8'h0; + mem_write_data = 32'h0; + end + endmodule // keywrap //====================================================================== diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v index 4d1c25c..1f1dabf 100644 --- a/src/tb/tb_keywrap.v +++ b/src/tb/tb_keywrap.v @@ -97,6 +97,10 @@ module tb_keywrap(); reg tb_clk; reg tb_reset_n; + wire tb_mkm_spi_sclk; + wire tb_mkm_spi_cs_n; + reg tb_mkm_spi_do; + wire tb_mkm_spi_di; reg tb_cs; reg tb_we; reg [(ADDR_BITS -1 ) : 0] tb_address; @@ -111,6 +115,10 @@ module tb_keywrap(); keywrap dut( .clk(tb_clk), .reset_n(tb_reset_n), + .mkm_spi_sclk(tb_mkm_spi_sclk), + .mkm_spi_cs_n(tb_mkm_spi_cs_n), + .mkm_spi_do(tb_mkm_spi_do), + .mkm_spi_di(tb_mkm_spi_di), .cs(tb_cs), .we(tb_we), .address(tb_address), @@ -330,15 +338,17 @@ module tb_keywrap(); //---------------------------------------------------------------- task init_sim; begin - cycle_ctr = 0; - error_ctr = 0; - tc_ctr = 0; + cycle_ctr = 1'h0; + error_ctr = 1'h0; + tc_ctr = 1'h0; - tb_clk = 0; - tb_reset_n = 1; + tb_clk = 1'h0; + tb_reset_n = 1'h1; - tb_cs = 0; - tb_we = 0; + tb_mkm_spi_do = 1'h1; + + tb_cs = 1'h0; + tb_we = 1'h0; tb_address = 8'h0; tb_write_data = 32'h0; end diff --git a/toolruns/Makefile b/toolruns/Makefile index 6a37c41..1ca960b 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -37,6 +37,9 @@ # #=================================================================== +MKMIF_PATH = ../../mkmif/src/rtl +MKMIF_SRC = $(MKMIF_PATH)/mkmif.v $(MKMIF_PATH)/mkmif_core.v $(MKMIF_PATH)/mkmif_spi.v + AES_PATH = ../../../../core/cipher/aes_speed/src/rtl AES_SRC = $(AES_PATH)/aes_core.v $(AES_PATH)/aes_decipher_block.v $(AES_PATH)/aes_encipher_block.v $(AES_PATH)/aes_inv_sbox.v $(AES_PATH)/aes_key_mem.v $(AES_PATH)/aes_sbox.v @@ -46,7 +49,7 @@ TB_MEM_SRC = ../src/tb/tb_keywrap_mem.v CORE_SRC = ../src/rtl/keywrap_core.v $(AES_SRC) $(MEM_SRC) TB_CORE_SRC = ../src/tb/tb_keywrap_core.v -TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) +TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) $(MKMIF_SRC) TB_TOP_SRC = ../src/tb/tb_keywrap.v CC = iverilog -- cgit v1.2.3 From 00fd27b23e578f5c92d856951645805be5dbab1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 18 Sep 2018 09:54:20 +0200 Subject: Moved the mkmif instance into the core itself. Added API to read the key if DEBUG is set. --- src/rtl/keywrap.v | 49 +++++++++++++----------------------------------- src/rtl/keywrap_core.v | 36 +++++++++++++++++++++++++++++++++++ src/tb/tb_keywrap_core.v | 10 ++++++++++ toolruns/Makefile | 4 ++-- 4 files changed, 61 insertions(+), 38 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index b394c9c..5604ce4 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -151,16 +151,11 @@ module keywrap #(parameter ADDR_BITS = 13) wire core_ready; wire core_valid; wire [255 : 0] core_key; + wire [255 : 0] core_read_key; wire [63 : 0] core_a_init; wire [63 : 0] core_a_result; wire [31 : 0] core_api_rd_data; - reg mem_cs; - reg mem_we; - reg [7 : 0] mem_address; - reg [31 : 0] mem_write_data; - wire [31 : 0] mem_read_data; - //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -184,6 +179,11 @@ module keywrap #(parameter ADDR_BITS = 13) .clk(clk), .reset_n(reset_n), + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), + .init(init_reg), .next(next_reg), .encdec(encdec_reg), @@ -195,6 +195,7 @@ module keywrap #(parameter ADDR_BITS = 13) .key(core_key), .keylen(keylen_reg), + .read_key(core_read_key), .a_init(core_a_init), .a_result(core_a_result), @@ -205,22 +206,6 @@ module keywrap #(parameter ADDR_BITS = 13) .api_rd_data(core_api_rd_data) ); - mkmif memory( - .clk(clk), - .reset_n(reset_n), - - .spi_sclk(mkm_spi_sclk), - .spi_cs_n(mkm_spi_cs_n), - .spi_do(mkm_spi_do), - .spi_di(mkm_spi_di), - - .cs(mem_cs), - .we(mem_we), - .address(mem_address), - .write_data(mem_write_data), - .read_data(mem_read_data) - ); - //---------------------------------------------------------------- // reg_update @@ -303,6 +288,7 @@ module keywrap #(parameter ADDR_BITS = 13) begin if (we) begin + // Write access if (address == {{PAD{1'h0}}, ADDR_CTRL}) begin init_new = write_data[CTRL_INIT_BIT]; @@ -354,23 +340,14 @@ module keywrap #(parameter ADDR_BITS = 13) if (address == {{PAD{1'h0}}, ADDR_A1}) api_rd_delay_new = core_a_result[31 : 0]; + + // Not correct read key mux. + if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && + (address <= {{PAD{1'h0}}, ADDR_KEY7})) + api_rd_delay_new = core_read_key[031 : 000]; end // else: !if(we) end // if (cs) end // block: api - - - //---------------------------------------------------------------- - // mkmif_ctrl - // Logic needed to handle the integratrion of the mkmif - //---------------------------------------------------------------- - always @* - begin : mkmif_ctrl - mem_cs = 1'h0; - mem_we = 1'h0; - mem_address = 8'h0; - mem_write_data = 32'h0; - end - endmodule // keywrap //====================================================================== diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index d1e63b0..e9a7177 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -45,6 +45,11 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire clk, input wire reset_n, + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + input wire init, input wire next, input wire encdec, @@ -56,6 +61,7 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire [255 : 0] key, input wire keylen, + output wire [255 : 0] read_key, input wire [63 : 0] a_init, output wire [63 : 0] a_result, @@ -84,6 +90,9 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam CTRL_NEXT_UCHECK = 4'h9; localparam CTRL_NEXT_FINALIZE = 4'ha; + // If set to one, will allow read access to key memory. + localparam DEBUG_MKM_READ = 1'h1; + //---------------------------------------------------------------- // Registers and memories including control signals. @@ -139,6 +148,12 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; + reg mkm_cs; + reg mkm_we; + reg [7 : 0] mkm_address; + reg [31 : 0] mkm_write_data; + wire [31 : 0] mkm_read_data; + //---------------------------------------------------------------- // Instantiations. @@ -178,6 +193,23 @@ module keywrap_core #(parameter MEM_BITS = 11) ); + mkmif mkm( + .clk(clk), + .reset_n(reset_n), + + .spi_sclk(mkm_spi_sclk), + .spi_cs_n(mkm_spi_cs_n), + .spi_do(mkm_spi_do), + .spi_di(mkm_spi_di), + + .cs(mkm_cs), + .we(mkm_we), + .address(mkm_address), + .write_data(mkm_write_data), + .read_data(mkm_read_data) + ); + + //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- @@ -356,6 +388,10 @@ module keywrap_core #(parameter MEM_BITS = 11) iteration_ctr_dec = 1'h0; iteration_ctr_set = 1'h0; iteration_ctr_rst = 1'h0; + mkm_cs = 1'h0; + mkm_we = 1'h0; + mkm_address = 8'h0; + mkm_write_data = 32'h0; keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h0; diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v index 17c8f30..358b512 100644 --- a/src/tb/tb_keywrap_core.v +++ b/src/tb/tb_keywrap_core.v @@ -77,6 +77,11 @@ module tb_keywrap_core(); reg [31 : 0] tb_api_wr_data; wire [31 : 0] tb_api_rd_data; + wire tb_mkm_spi_sclk; + wire tb_mkm_spi_cs_n; + reg tb_mkm_spi_do; + wire tb_mkm_spi_di; + //---------------------------------------------------------------- // Device Under Test. @@ -86,6 +91,11 @@ module tb_keywrap_core(); .clk(tb_clk), .reset_n(tb_reset_n), + .mkm_spi_sclk(tb_mkm_spi_sclk), + .mkm_spi_cs_n(tb_mkm_spi_cs_n), + .mkm_spi_do(tb_mkm_spi_do), + .mkm_spi_di(tb_mkm_spi_di), + .init(tb_init), .next(tb_next), .encdec(tb_encdec), diff --git a/toolruns/Makefile b/toolruns/Makefile index 1ca960b..3ea00bd 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -46,10 +46,10 @@ AES_SRC = $(AES_PATH)/aes_core.v $(AES_PATH)/aes_decipher_block.v $(AES_PATH)/ae MEM_SRC = ../src/rtl/keywrap_mem.v TB_MEM_SRC = ../src/tb/tb_keywrap_mem.v -CORE_SRC = ../src/rtl/keywrap_core.v $(AES_SRC) $(MEM_SRC) +CORE_SRC = ../src/rtl/keywrap_core.v $(AES_SRC) $(MEM_SRC) $(MKMIF_SRC) TB_CORE_SRC = ../src/tb/tb_keywrap_core.v -TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) $(MKMIF_SRC) +TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) TB_TOP_SRC = ../src/tb/tb_keywrap.v CC = iverilog -- cgit v1.2.3 From 50bc6e775d7a2a4ad75511c43af93759cc6b09c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 18 Sep 2018 11:19:30 +0200 Subject: Moved compile time debug access control of key to the API. Added correct code to mux key. --- src/rtl/keywrap.v | 15 +++++++++++---- src/rtl/keywrap_core.v | 3 --- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index 5604ce4..786ab54 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -108,6 +108,11 @@ module keywrap #(parameter ADDR_BITS = 13) localparam PAD = ADDR_BITS - 8; + // If set to one, will allow read access to key memory. + // Should be set to zero in all production FPGA bitstreams. + localparam DEBUG_MKM_READ = 1'h1; + + //---------------------------------------------------------------- // Registers including update variables and write enable. //---------------------------------------------------------------- @@ -341,10 +346,12 @@ module keywrap #(parameter ADDR_BITS = 13) if (address == {{PAD{1'h0}}, ADDR_A1}) api_rd_delay_new = core_a_result[31 : 0]; - // Not correct read key mux. - if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && - (address <= {{PAD{1'h0}}, ADDR_KEY7})) - api_rd_delay_new = core_read_key[031 : 000]; + // Warning: Should be disabled after mkmif + // integration has been completed. + if (DEBUG_MKM_READ) + if ((address >= {{PAD{1'h0}},ADDR_KEY0}) && (address <= {{PAD{1'h0}}, ADDR_KEY7})) + api_rd_delay_new = core_read_key[(7 - (address - {{PAD{1'h0}}, ADDR_KEY7})) * 32 +: 32]; + end // else: !if(we) end // if (cs) end // block: api diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index e9a7177..6810307 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -90,9 +90,6 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam CTRL_NEXT_UCHECK = 4'h9; localparam CTRL_NEXT_FINALIZE = 4'ha; - // If set to one, will allow read access to key memory. - localparam DEBUG_MKM_READ = 1'h1; - //---------------------------------------------------------------- // Registers and memories including control signals. -- cgit v1.2.3 From 12db6151bf7a1c896a6f4bb37d46992a3621caaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 18 Sep 2018 12:35:29 +0200 Subject: Adding API control bits to read and write key. --- src/rtl/keywrap.v | 24 +++++++++++++++++++++--- src/rtl/keywrap_core.v | 2 ++ src/tb/tb_keywrap_core.v | 8 +++++++- 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index 786ab54..870a85c 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -77,6 +77,8 @@ module keywrap #(parameter ADDR_BITS = 13) localparam ADDR_CTRL = 8'h08; localparam CTRL_INIT_BIT = 0; localparam CTRL_NEXT_BIT = 1; + localparam CTRL_READ_BIT = 2; + localparam CTRL_WRITE_BIT = 3; localparam ADDR_STATUS = 8'h09; localparam STATUS_READY_BIT = 0; @@ -122,6 +124,12 @@ module keywrap #(parameter ADDR_BITS = 13) reg next_reg; reg next_new; + reg read_reg; + reg read_new; + + reg write_reg; + reg write_new; + reg encdec_reg; reg keylen_reg; reg config_we; @@ -191,6 +199,8 @@ module keywrap #(parameter ADDR_BITS = 13) .init(init_reg), .next(next_reg), + .read(read_reg), + .write(write_reg), .encdec(encdec_reg), .ready(core_ready), @@ -226,6 +236,8 @@ module keywrap #(parameter ADDR_BITS = 13) init_reg <= 1'h0; next_reg <= 1'h0; + read_reg <= 1'h0; + write_reg <= 1'h0; encdec_reg <= 1'h0; keylen_reg <= 1'h0; rlen_reg <= {RLEN_BITS{1'h0}}; @@ -241,6 +253,8 @@ module keywrap #(parameter ADDR_BITS = 13) valid_reg <= core_valid; init_reg <= init_new; next_reg <= next_new; + read_reg <= read_new; + write_reg <= write_new; api_rd_delay_reg <= api_rd_delay_new; if (config_we) @@ -273,6 +287,8 @@ module keywrap #(parameter ADDR_BITS = 13) begin : api init_new = 1'h0; next_new = 1'h0; + read_new = 1'h0; + write_new = 1'h0; config_we = 1'h0; rlen_we = 1'h0; key_we = 1'h0; @@ -296,8 +312,10 @@ module keywrap #(parameter ADDR_BITS = 13) // Write access if (address == {{PAD{1'h0}}, ADDR_CTRL}) begin - init_new = write_data[CTRL_INIT_BIT]; - next_new = write_data[CTRL_NEXT_BIT]; + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + read_new = write_data[CTRL_READ_BIT]; + write_new = write_data[CTRL_WRITE_BIT]; end if (address == {{PAD{1'h0}}, ADDR_CONFIG}) @@ -332,7 +350,7 @@ module keywrap #(parameter ADDR_BITS = 13) api_rd_delay_new = CORE_VERSION; if (address == {{PAD{1'h0}}, ADDR_CTRL}) - api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg}; + api_rd_delay_new = {26'h0, keylen_reg, encdec_reg, write_reg, read_reg, next_reg, init_reg}; if (address == {{PAD{1'h0}}, ADDR_STATUS}) api_rd_delay_new = {30'h0, valid_reg, ready_reg}; diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 6810307..9c2fa50 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -52,6 +52,8 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire init, input wire next, + input wire read, + input wire write, input wire encdec, output wire ready, diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v index 358b512..4b94b26 100644 --- a/src/tb/tb_keywrap_core.v +++ b/src/tb/tb_keywrap_core.v @@ -64,6 +64,8 @@ module tb_keywrap_core(); reg tb_reset_n; reg tb_init; reg tb_next; + reg tb_read; + reg tb_write; reg tb_encdec; wire tb_ready; wire tb_valid; @@ -98,7 +100,9 @@ module tb_keywrap_core(); .init(tb_init), .next(tb_next), - .encdec(tb_encdec), + .read(tb_read), + .write(tb_write), + .encdec(tb_encdec), .ready(tb_ready), .valid(tb_valid), @@ -159,6 +163,8 @@ module tb_keywrap_core(); tb_init = 0; tb_next = 0; + tb_read = 0; + tb_write = 0; tb_encdec = 0; tb_rlen = 13'h0; tb_key = 256'h0; -- cgit v1.2.3 From aefd88d9fbc525e4d3dc56b9e01e5ff21f9c1ff2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 18 Sep 2018 12:51:19 +0200 Subject: Increasing control state reg to support more states. Adding first states for read and write key handling. --- src/rtl/keywrap_core.v | 78 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 65 insertions(+), 13 deletions(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 9c2fa50..c517757 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -80,17 +80,21 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- localparam MAX_ITERATIONS = 6 - 1; - localparam CTRL_IDLE = 4'h0; - localparam CTRL_INIT_WAIT = 4'h1; - localparam CTRL_NEXT_WSTART = 4'h2; - localparam CTRL_NEXT_USTART = 4'h3; - localparam CTRL_NEXT_LOOP0 = 4'h4; - localparam CTRL_NEXT_LOOP = 4'h5; - localparam CTRL_NEXT_WAIT = 4'h6; - localparam CTRL_NEXT_UPDATE = 4'h7; - localparam CTRL_NEXT_WCHECK = 4'h8; - localparam CTRL_NEXT_UCHECK = 4'h9; - localparam CTRL_NEXT_FINALIZE = 4'ha; + localparam CTRL_IDLE = 5'h0; + localparam CTRL_INIT_WAIT = 5'h1; + localparam CTRL_NEXT_WSTART = 5'h2; + localparam CTRL_NEXT_USTART = 5'h3; + localparam CTRL_NEXT_LOOP0 = 5'h4; + localparam CTRL_NEXT_LOOP = 5'h5; + localparam CTRL_NEXT_WAIT = 5'h6; + localparam CTRL_NEXT_UPDATE = 5'h7; + localparam CTRL_NEXT_WCHECK = 5'h8; + localparam CTRL_NEXT_UCHECK = 5'h9; + localparam CTRL_NEXT_FINALIZE = 5'ha; + localparam CTRL_READ_START = 5'h10; + localparam CTRL_READ_END = 5'h11; + localparam CTRL_WRITE_START = 5'h18; + localparam CTRL_WRITE_END = 5'h19; //---------------------------------------------------------------- @@ -125,8 +129,8 @@ module keywrap_core #(parameter MEM_BITS = 11) reg iteration_ctr_set; reg iteration_ctr_rst; - reg [3 : 0] keywrap_core_ctrl_reg; - reg [3 : 0] keywrap_core_ctrl_new; + reg [4 : 0] keywrap_core_ctrl_reg; + reg [4 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; @@ -423,6 +427,22 @@ module keywrap_core #(parameter MEM_BITS = 11) keywrap_core_ctrl_new = CTRL_NEXT_USTART; keywrap_core_ctrl_we = 1'h1; end + + if (read) + begin + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_READ_START; + keywrap_core_ctrl_we = 1'h1; + end + + if (write) + begin + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_WRITE_START; + keywrap_core_ctrl_we = 1'h1; + end end @@ -553,6 +573,38 @@ module keywrap_core #(parameter MEM_BITS = 11) keywrap_core_ctrl_we = 1'h1; end + + CTRL_READ_START: + begin + keywrap_core_ctrl_new = CTRL_READ_END; + keywrap_core_ctrl_we = 1'h1; + end + + + CTRL_READ_END: + begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_IDLE; + keywrap_core_ctrl_we = 1'h1; + end + + + CTRL_WRITE_START: + begin + keywrap_core_ctrl_new = CTRL_WRITE_END; + keywrap_core_ctrl_we = 1'h1; + end + + + CTRL_WRITE_END: + begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_IDLE; + keywrap_core_ctrl_we = 1'h1; + end + default: begin -- cgit v1.2.3 From 0c7becd454c9daf400eaff51978e7a27ed88f6c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 18 Sep 2018 14:44:39 +0200 Subject: Adding more functionality needed for the mkm integration. --- src/rtl/keywrap_core.v | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index c517757..9ae1e75 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -96,6 +96,21 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam CTRL_WRITE_START = 5'h18; localparam CTRL_WRITE_END = 5'h19; + // API for mkm used by the core. + localparam MKM_ADDR_CTRL = 8'h08; + localparam MKM_CTRL_READ_BIT = 0; + localparam MKM_CTRL_WRITE_BIT = 1; + localparam MKM_ADDR_STATUS = 8'h09; + localparam MKM_STATUS_READY_BIT = 0; + localparam MKM_STATUS_VALID_BIT = 1; + localparam MKM_ADDR_SCLK_DIV = 8'h0a; + localparam MKM_ADDR_EMEM_ADDR = 8'h10; + localparam MKM_ADDR_EMEM_DATA = 8'h20; + + // Addresses for storage in the mkm + localparam MKM_STATUS_WORD = 8'h00; + localparam MKM_KEY_BASE_WORD = 8'h04; + //---------------------------------------------------------------- // Registers and memories including control signals. @@ -129,6 +144,17 @@ module keywrap_core #(parameter MEM_BITS = 11) reg iteration_ctr_set; reg iteration_ctr_rst; + reg [31 : 0] core_key [0 : 7]; + reg core_key_we; + + reg [2 : 0] mkm_word_ctr_reg; + reg [2 : 0] mkm_word_ctr_new; + reg mkm_word_ctr_we; + + reg [7 : 0] mkm_addr_reg; + reg [7 : 0] mkm_addr_new; + reg mkm_addr_we; + reg [4 : 0] keywrap_core_ctrl_reg; reg [4 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; @@ -226,13 +252,20 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin: reg_update + integer i; + if (!reset_n) begin + for (i = 0 ; i < 8 ; i = i + 1) + core_key[i] <= 32'h0; + a_reg <= 64'h0; ready_reg <= 1'h1; valid_reg <= 1'h1; block_ctr_reg <= {(MEM_BITS - 1){1'h0}}; iteration_ctr_reg <= 3'h0; + mkm_word_ctr_reg <= 3'h0; + mkm_addr_reg <= 8'h0; keywrap_core_ctrl_reg <= CTRL_IDLE; end -- cgit v1.2.3 From 241f9157a534a6f9d953fe06273e2abe2693f4ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 21 Sep 2018 16:54:47 +0200 Subject: Adding more infrastructure needed for the integrated mkm. --- src/rtl/keywrap_core.v | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 9ae1e75..9f9b329 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -64,6 +64,7 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire [255 : 0] key, input wire keylen, output wire [255 : 0] read_key, + output wire [31 : 0] mkm_status, input wire [63 : 0] a_init, output wire [63 : 0] a_result, @@ -144,8 +145,8 @@ module keywrap_core #(parameter MEM_BITS = 11) reg iteration_ctr_set; reg iteration_ctr_rst; - reg [31 : 0] core_key [0 : 7]; - reg core_key_we; + reg [31 : 0] mkm_key [0 : 7]; + reg mkm_key_we; reg [2 : 0] mkm_word_ctr_reg; reg [2 : 0] mkm_word_ctr_new; @@ -155,6 +156,10 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [7 : 0] mkm_addr_new; reg mkm_addr_we; + reg [31 : 0] mkm_status_reg; + reg [31 : 0] mkm_status_new; + reg mkm_status_we; + reg [4 : 0] keywrap_core_ctrl_reg; reg [4 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; @@ -242,9 +247,10 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- - assign a_result = a_reg; - assign ready = ready_reg; - assign valid = valid_reg; + assign a_result = a_reg; + assign ready = ready_reg; + assign valid = valid_reg; + assign mkm_status = mkm_status_reg; //---------------------------------------------------------------- @@ -257,7 +263,7 @@ module keywrap_core #(parameter MEM_BITS = 11) if (!reset_n) begin for (i = 0 ; i < 8 ; i = i + 1) - core_key[i] <= 32'h0; + mkm_key[i] <= 32'h0; a_reg <= 64'h0; ready_reg <= 1'h1; @@ -266,6 +272,7 @@ module keywrap_core #(parameter MEM_BITS = 11) iteration_ctr_reg <= 3'h0; mkm_word_ctr_reg <= 3'h0; mkm_addr_reg <= 8'h0; + mkm_status_reg <= 32'h0; keywrap_core_ctrl_reg <= CTRL_IDLE; end @@ -274,6 +281,9 @@ module keywrap_core #(parameter MEM_BITS = 11) if (a_we) a_reg <= a_new; + if (mkm_status_we) + mkm_status_reg <= mkm_read_data; + if (ready_we) ready_reg <= ready_new; @@ -428,6 +438,9 @@ module keywrap_core #(parameter MEM_BITS = 11) mkm_we = 1'h0; mkm_address = 8'h0; mkm_write_data = 32'h0; + mkm_word_ctr_we = 1'h0; + mkm_status_we = 1'h0; + keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h0; -- cgit v1.2.3 From 384b029659d9205b32b2d9707c2fa24c554d0b27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 25 Sep 2018 13:44:06 +0200 Subject: Integrate the mkmif_core instead of the mkmif wrapper. --- src/rtl/keywrap_core.v | 55 +++++++++++++++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 9f9b329..178cea1 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -112,6 +112,8 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam MKM_STATUS_WORD = 8'h00; localparam MKM_KEY_BASE_WORD = 8'h04; + localparam DEFAULT_SCLK_DIV = 16'h0020; + //---------------------------------------------------------------- // Registers and memories including control signals. @@ -182,9 +184,13 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; - reg mkm_cs; - reg mkm_we; - reg [7 : 0] mkm_address; + reg mkm_init_op; + reg mkm_read_op; + reg mkm_write_op; + wire mkm_ready; + wire mkm_valid; + reg [15 : 0] mkm_sclk_div; + reg [15 : 0] mkm_addr; reg [31 : 0] mkm_write_data; wire [31 : 0] mkm_read_data; @@ -227,21 +233,27 @@ module keywrap_core #(parameter MEM_BITS = 11) ); - mkmif mkm( - .clk(clk), - .reset_n(reset_n), + mkmif_core mkm( + .clk(clk), + .reset_n(reset_n), + + .spi_sclk(mkm_spi_sclk), + .spi_cs_n(mkm_spi_cs_n), + .spi_do(mkm_spi_do), + .spi_di(mkm_spi_di), - .spi_sclk(mkm_spi_sclk), - .spi_cs_n(mkm_spi_cs_n), - .spi_do(mkm_spi_do), - .spi_di(mkm_spi_di), + .init_op(mkm_init_op), + .read_op(mkm_read_op), + .write_op(mkm_write_op), - .cs(mkm_cs), - .we(mkm_we), - .address(mkm_address), - .write_data(mkm_write_data), - .read_data(mkm_read_data) - ); + .ready(mkm_ready), + .valid(mkm_valid), + + .sclk_div(mkm_sclk_div), + .addr(mkm_addr), + .write_data(mkm_write_data), + .read_data(mkm_read_data) + ); //---------------------------------------------------------------- @@ -434,12 +446,13 @@ module keywrap_core #(parameter MEM_BITS = 11) iteration_ctr_dec = 1'h0; iteration_ctr_set = 1'h0; iteration_ctr_rst = 1'h0; - mkm_cs = 1'h0; - mkm_we = 1'h0; - mkm_address = 8'h0; + + mkm_init_op = 1'h0; + mkm_read_op = 1'h0; + mkm_write_op = 1'h0; + mkm_sclk_div = DEFAULT_SCLK_DIV; + mkm_addr = 16'h0; mkm_write_data = 32'h0; - mkm_word_ctr_we = 1'h0; - mkm_status_we = 1'h0; keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h0; -- cgit v1.2.3 From 139b3e484d9d170c739498bc9de7ee8106af9c55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 25 Sep 2018 14:09:49 +0200 Subject: Increased control state space to make room for read and write operations. --- src/rtl/keywrap_core.v | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 178cea1..5a05b63 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -81,21 +81,21 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- localparam MAX_ITERATIONS = 6 - 1; - localparam CTRL_IDLE = 5'h0; - localparam CTRL_INIT_WAIT = 5'h1; - localparam CTRL_NEXT_WSTART = 5'h2; - localparam CTRL_NEXT_USTART = 5'h3; - localparam CTRL_NEXT_LOOP0 = 5'h4; - localparam CTRL_NEXT_LOOP = 5'h5; - localparam CTRL_NEXT_WAIT = 5'h6; - localparam CTRL_NEXT_UPDATE = 5'h7; - localparam CTRL_NEXT_WCHECK = 5'h8; - localparam CTRL_NEXT_UCHECK = 5'h9; - localparam CTRL_NEXT_FINALIZE = 5'ha; - localparam CTRL_READ_START = 5'h10; - localparam CTRL_READ_END = 5'h11; - localparam CTRL_WRITE_START = 5'h18; - localparam CTRL_WRITE_END = 5'h19; + localparam CTRL_IDLE = 6'h0; + localparam CTRL_INIT_WAIT = 6'h1; + localparam CTRL_NEXT_WSTART = 6'h2; + localparam CTRL_NEXT_USTART = 6'h3; + localparam CTRL_NEXT_LOOP0 = 6'h4; + localparam CTRL_NEXT_LOOP = 6'h5; + localparam CTRL_NEXT_WAIT = 6'h6; + localparam CTRL_NEXT_UPDATE = 6'h7; + localparam CTRL_NEXT_WCHECK = 6'h8; + localparam CTRL_NEXT_UCHECK = 6'h9; + localparam CTRL_NEXT_FINALIZE = 6'ha; + localparam CTRL_READ_START = 6'h10; + localparam CTRL_READ_END = 6'h11; + localparam CTRL_WRITE_START = 6'h18; + localparam CTRL_WRITE_END = 6'h19; // API for mkm used by the core. localparam MKM_ADDR_CTRL = 8'h08; @@ -162,8 +162,8 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [31 : 0] mkm_status_new; reg mkm_status_we; - reg [4 : 0] keywrap_core_ctrl_reg; - reg [4 : 0] keywrap_core_ctrl_new; + reg [5 : 0] keywrap_core_ctrl_reg; + reg [5 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; -- cgit v1.2.3 From d3e94a0efeec9b2cbac41eea9a57dc3eaf848b21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 25 Sep 2018 14:35:35 +0200 Subject: Updated the keywrap API to support access to MKM status. Updated keywrap_core to support control of MKM access operations. --- src/rtl/keywrap.v | 101 ++++++++++++++++++++++++++++--------------------- src/rtl/keywrap_core.v | 52 +++++++++++++------------ 2 files changed, 85 insertions(+), 68 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index 870a85c..829ddd1 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -70,44 +70,47 @@ module keywrap #(parameter ADDR_BITS = 13) //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; - - localparam ADDR_CTRL = 8'h08; - localparam CTRL_INIT_BIT = 0; - localparam CTRL_NEXT_BIT = 1; - localparam CTRL_READ_BIT = 2; - localparam CTRL_WRITE_BIT = 3; - - localparam ADDR_STATUS = 8'h09; - localparam STATUS_READY_BIT = 0; - localparam STATUS_VALID_BIT = 1; - - localparam ADDR_CONFIG = 8'h0a; - localparam CTRL_ENCDEC_BIT = 0; - localparam CTRL_KEYLEN_BIT = 1; - - localparam ADDR_RLEN = 8'h0c; - localparam ADDR_A0 = 8'h0e; - localparam ADDR_A1 = 8'h0f; - - localparam ADDR_KEY0 = 8'h10; - localparam ADDR_KEY1 = 8'h11; - localparam ADDR_KEY2 = 8'h12; - localparam ADDR_KEY3 = 8'h13; - localparam ADDR_KEY4 = 8'h14; - localparam ADDR_KEY5 = 8'h15; - localparam ADDR_KEY6 = 8'h16; - localparam ADDR_KEY7 = 8'h17; - - localparam CORE_NAME0 = 32'h6b657920; // "key " - localparam CORE_NAME1 = 32'h77726170; // "wrap" - localparam CORE_VERSION = 32'h302e3830; // "0.80" - - localparam MEM_BITS = ADDR_BITS - 1; - localparam RLEN_BITS = ADDR_BITS - 2; - localparam PAD = ADDR_BITS - 8; + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; + + localparam ADDR_CTRL = 8'h08; + localparam CTRL_INIT_BIT = 0; + localparam CTRL_NEXT_BIT = 1; + localparam CTRL_READ_BIT = 2; + localparam CTRL_WRITE_BIT = 3; + + localparam ADDR_STATUS = 8'h09; + localparam STATUS_READY_BIT = 0; + localparam STATUS_VALID_BIT = 1; + + localparam ADDR_CONFIG = 8'h0a; + localparam CONFIG_ENCDEC_BIT = 0; + localparam CONFIG_KEYLEN_BIT = 1; + localparam CONFIG_MKS_BIT = 2; + + localparam ADDR_RLEN = 8'h0c; + localparam ADDR_A0 = 8'h0e; + localparam ADDR_A1 = 8'h0f; + + localparam ADDR_KEY0 = 8'h10; + localparam ADDR_KEY1 = 8'h11; + localparam ADDR_KEY2 = 8'h12; + localparam ADDR_KEY3 = 8'h13; + localparam ADDR_KEY4 = 8'h14; + localparam ADDR_KEY5 = 8'h15; + localparam ADDR_KEY6 = 8'h16; + localparam ADDR_KEY7 = 8'h17; + + localparam ADDR_MSTATUS = 8'h20; + + localparam CORE_NAME0 = 32'h6b657920; // "key " + localparam CORE_NAME1 = 32'h77726170; // "wrap" + localparam CORE_VERSION = 32'h302e3830; // "0.80" + + localparam MEM_BITS = ADDR_BITS - 1; + localparam RLEN_BITS = ADDR_BITS - 2; + localparam PAD = ADDR_BITS - 8; // If set to one, will allow read access to key memory. @@ -130,6 +133,9 @@ module keywrap #(parameter ADDR_BITS = 13) reg write_reg; reg write_new; + reg mkey_mstatus_reg; + reg mkey_mstatus_new; + reg encdec_reg; reg keylen_reg; reg config_we; @@ -164,7 +170,8 @@ module keywrap #(parameter ADDR_BITS = 13) wire core_ready; wire core_valid; wire [255 : 0] core_key; - wire [255 : 0] core_read_key; + wire [255 : 0] core_mkey; + wire [31 : 0] core_mstatus; wire [63 : 0] core_a_init; wire [63 : 0] core_a_result; wire [31 : 0] core_api_rd_data; @@ -201,6 +208,7 @@ module keywrap #(parameter ADDR_BITS = 13) .next(next_reg), .read(read_reg), .write(write_reg), + .mkey_mstatus(mkey_mstatus_reg), .encdec(encdec_reg), .ready(core_ready), @@ -210,7 +218,8 @@ module keywrap #(parameter ADDR_BITS = 13) .key(core_key), .keylen(keylen_reg), - .read_key(core_read_key), + .mkey(core_mkey), + .mstatus(core_mstatus), .a_init(core_a_init), .a_result(core_a_result), @@ -238,6 +247,7 @@ module keywrap #(parameter ADDR_BITS = 13) next_reg <= 1'h0; read_reg <= 1'h0; write_reg <= 1'h0; + mkey_mstatus_reg <= 1'h0; encdec_reg <= 1'h0; keylen_reg <= 1'h0; rlen_reg <= {RLEN_BITS{1'h0}}; @@ -255,12 +265,14 @@ module keywrap #(parameter ADDR_BITS = 13) next_reg <= next_new; read_reg <= read_new; write_reg <= write_new; + mkey_mstatus_reg <= mkey_mstatus_new; api_rd_delay_reg <= api_rd_delay_new; if (config_we) begin - encdec_reg <= write_data[CTRL_ENCDEC_BIT]; - keylen_reg <= write_data[CTRL_KEYLEN_BIT]; + mkey_mstatus_reg <= write_data[CONFIG_MKS_BIT]; + encdec_reg <= write_data[CONFIG_ENCDEC_BIT]; + keylen_reg <= write_data[CONFIG_KEYLEN_BIT]; end if (rlen_we) @@ -364,11 +376,14 @@ module keywrap #(parameter ADDR_BITS = 13) if (address == {{PAD{1'h0}}, ADDR_A1}) api_rd_delay_new = core_a_result[31 : 0]; + if (address == {{PAD{1'h0}}, ADDR_MSTATUS}) + api_rd_delay_new = core_mstatus; + // Warning: Should be disabled after mkmif // integration has been completed. if (DEBUG_MKM_READ) if ((address >= {{PAD{1'h0}},ADDR_KEY0}) && (address <= {{PAD{1'h0}}, ADDR_KEY7})) - api_rd_delay_new = core_read_key[(7 - (address - {{PAD{1'h0}}, ADDR_KEY7})) * 32 +: 32]; + api_rd_delay_new = core_mkey[(7 - (address - {{PAD{1'h0}}, ADDR_KEY7})) * 32 +: 32]; end // else: !if(we) end // if (cs) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 5a05b63..8688e31 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -54,6 +54,7 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire next, input wire read, input wire write, + input wire mkey_mstatus, input wire encdec, output wire ready, @@ -63,8 +64,8 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire [255 : 0] key, input wire keylen, - output wire [255 : 0] read_key, - output wire [31 : 0] mkm_status, + output wire [255 : 0] mkey, + output wire [31 : 0] mstatus, input wire [63 : 0] a_init, output wire [63 : 0] a_result, @@ -81,21 +82,22 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- localparam MAX_ITERATIONS = 6 - 1; - localparam CTRL_IDLE = 6'h0; - localparam CTRL_INIT_WAIT = 6'h1; - localparam CTRL_NEXT_WSTART = 6'h2; - localparam CTRL_NEXT_USTART = 6'h3; - localparam CTRL_NEXT_LOOP0 = 6'h4; - localparam CTRL_NEXT_LOOP = 6'h5; - localparam CTRL_NEXT_WAIT = 6'h6; - localparam CTRL_NEXT_UPDATE = 6'h7; - localparam CTRL_NEXT_WCHECK = 6'h8; - localparam CTRL_NEXT_UCHECK = 6'h9; - localparam CTRL_NEXT_FINALIZE = 6'ha; - localparam CTRL_READ_START = 6'h10; - localparam CTRL_READ_END = 6'h11; - localparam CTRL_WRITE_START = 6'h18; - localparam CTRL_WRITE_END = 6'h19; + localparam CTRL_IDLE = 6'h0; + localparam CTRL_INIT_WAIT = 6'h1; + localparam CTRL_NEXT_WSTART = 6'h2; + localparam CTRL_NEXT_USTART = 6'h3; + localparam CTRL_NEXT_LOOP0 = 6'h4; + localparam CTRL_NEXT_LOOP = 6'h5; + localparam CTRL_NEXT_WAIT = 6'h6; + localparam CTRL_NEXT_UPDATE = 6'h7; + localparam CTRL_NEXT_WCHECK = 6'h8; + localparam CTRL_NEXT_UCHECK = 6'h9; + localparam CTRL_NEXT_FINALIZE = 6'ha; + + localparam CTRL_MKM_RD_START = 6'h10; + localparam CTRL_MKM_RD_END = 6'h11; + localparam CTRL_MKM_WR_START = 6'h18; + localparam CTRL_MKM_WR_END = 6'h19; // API for mkm used by the core. localparam MKM_ADDR_CTRL = 8'h08; @@ -491,7 +493,7 @@ module keywrap_core #(parameter MEM_BITS = 11) begin ready_new = 1'h0; ready_we = 1'h1; - keywrap_core_ctrl_new = CTRL_READ_START; + keywrap_core_ctrl_new = CTRL_MKM_RD_START; keywrap_core_ctrl_we = 1'h1; end @@ -499,7 +501,7 @@ module keywrap_core #(parameter MEM_BITS = 11) begin ready_new = 1'h0; ready_we = 1'h1; - keywrap_core_ctrl_new = CTRL_WRITE_START; + keywrap_core_ctrl_new = CTRL_MKM_WR_START; keywrap_core_ctrl_we = 1'h1; end end @@ -633,14 +635,14 @@ module keywrap_core #(parameter MEM_BITS = 11) end - CTRL_READ_START: + CTRL_MKM_RD_START: begin - keywrap_core_ctrl_new = CTRL_READ_END; + keywrap_core_ctrl_new = CTRL_MKM_RD_END; keywrap_core_ctrl_we = 1'h1; end - CTRL_READ_END: + CTRL_MKM_RD_END: begin ready_new = 1'h1; ready_we = 1'h1; @@ -649,14 +651,14 @@ module keywrap_core #(parameter MEM_BITS = 11) end - CTRL_WRITE_START: + CTRL_MKM_WR_START: begin - keywrap_core_ctrl_new = CTRL_WRITE_END; + keywrap_core_ctrl_new = CTRL_MKM_WR_END; keywrap_core_ctrl_we = 1'h1; end - CTRL_WRITE_END: + CTRL_MKM_WR_END: begin ready_new = 1'h1; ready_we = 1'h1; -- cgit v1.2.3 From aa31953d8789a7349970809955ee3a2f0ab78177 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 25 Sep 2018 15:08:30 +0200 Subject: Added logic to perform status word read operation from the mkm. Adding interfaces and registers to be able to pass mkm status to host. Updated dut instantiation in core testbench to. --- src/rtl/keywrap.v | 12 +++++++++ src/rtl/keywrap_core.v | 65 ++++++++++++++++++++++++++++++++++++++++++------ src/tb/tb_keywrap_core.v | 36 +++++++++++++++++---------- 3 files changed, 92 insertions(+), 21 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index 829ddd1..cc6f8ac 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -152,6 +152,9 @@ module keywrap #(parameter ADDR_BITS = 13) reg [31 : 0] key_reg [0 : 7]; reg key_we; + reg [31 : 0] mstatus_reg; + reg mstatus_we; + reg [31 : 0] api_rd_delay_reg; reg [31 : 0] api_rd_delay_new; @@ -218,6 +221,7 @@ module keywrap #(parameter ADDR_BITS = 13) .key(core_key), .keylen(keylen_reg), + .status(mstatus_reg), .mkey(core_mkey), .mstatus(core_mstatus), @@ -250,6 +254,7 @@ module keywrap #(parameter ADDR_BITS = 13) mkey_mstatus_reg <= 1'h0; encdec_reg <= 1'h0; keylen_reg <= 1'h0; + mstatus_reg <= 32'h0; rlen_reg <= {RLEN_BITS{1'h0}}; valid_reg <= 1'h0; ready_reg <= 1'h0; @@ -284,6 +289,9 @@ module keywrap #(parameter ADDR_BITS = 13) if (a1_we) a1_reg <= write_data; + if (mstatus_we) + mstatus_reg <= write_data; + if (key_we) key_reg[address[2 : 0]] <= write_data; end @@ -307,6 +315,7 @@ module keywrap #(parameter ADDR_BITS = 13) core_api_we = 1'h0; a0_we = 1'h0; a1_we = 1'h0; + mstatus_we = 1'h0; tmp_read_data = 32'h0; tmp_error = 1'h0; api_rd_delay_new = 32'h0; @@ -342,6 +351,9 @@ module keywrap #(parameter ADDR_BITS = 13) if (address == {{PAD{1'h0}}, ADDR_A1}) a1_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_MSTATUS}) + mstatus_we = 1'h1; + if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && (address <= {{PAD{1'h0}}, ADDR_KEY7})) key_we = 1'h1; diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 8688e31..00e8391 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -61,9 +61,9 @@ module keywrap_core #(parameter MEM_BITS = 11) output wire valid, input wire [(MEM_BITS - 2) : 0] rlen, - input wire [255 : 0] key, input wire keylen, + input wire [31 : 0] status, output wire [255 : 0] mkey, output wire [31 : 0] mstatus, @@ -95,9 +95,13 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam CTRL_NEXT_FINALIZE = 6'ha; localparam CTRL_MKM_RD_START = 6'h10; - localparam CTRL_MKM_RD_END = 6'h11; + localparam CTRL_MKM_RD_WAIT0 = 6'h11; + localparam CTRL_MKM_RD_STATUS = 6'h12; + localparam CTRL_MKM_RD_END = 6'h13; + localparam CTRL_MKM_WR_START = 6'h18; - localparam CTRL_MKM_WR_END = 6'h19; + localparam CTRL_MKM_WR_WAIT0 = 6'h19; + localparam CTRL_MKM_WR_END = 6'h1a; // API for mkm used by the core. localparam MKM_ADDR_CTRL = 8'h08; @@ -111,8 +115,8 @@ module keywrap_core #(parameter MEM_BITS = 11) localparam MKM_ADDR_EMEM_DATA = 8'h20; // Addresses for storage in the mkm - localparam MKM_STATUS_WORD = 8'h00; - localparam MKM_KEY_BASE_WORD = 8'h04; + localparam MKM_STATUS_WORD = 16'h00; + localparam MKM_KEY_BASE_WORD = 16'h04; localparam DEFAULT_SCLK_DIV = 16'h0020; @@ -264,7 +268,7 @@ module keywrap_core #(parameter MEM_BITS = 11) assign a_result = a_reg; assign ready = ready_reg; assign valid = valid_reg; - assign mkm_status = mkm_status_reg; + assign mstatus = mkm_status_reg; //---------------------------------------------------------------- @@ -637,11 +641,45 @@ module keywrap_core #(parameter MEM_BITS = 11) CTRL_MKM_RD_START: begin - keywrap_core_ctrl_new = CTRL_MKM_RD_END; + mkm_init_op = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_RD_WAIT0; keywrap_core_ctrl_we = 1'h1; end + CTRL_MKM_RD_WAIT0: + begin + if (mkm_ready) + // MKM should have been initialized. + if (mkey_mstatus) + begin + // Read master key from mkm. + keywrap_core_ctrl_new = CTRL_MKM_RD_END; + keywrap_core_ctrl_we = 1'h1; + end + else + begin + // Read master key status from mkm. + mkm_read_op = 1'h1; + mkm_addr = MKM_STATUS_WORD; + keywrap_core_ctrl_new = CTRL_MKM_RD_STATUS; + keywrap_core_ctrl_we = 1'h1; + end + end + + + CTRL_MKM_RD_STATUS: + begin + if (mkm_ready) + begin + // status should have been read. + mkm_status_we = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_RD_END; + keywrap_core_ctrl_we = 1'h1; + end + end + + CTRL_MKM_RD_END: begin ready_new = 1'h1; @@ -653,11 +691,22 @@ module keywrap_core #(parameter MEM_BITS = 11) CTRL_MKM_WR_START: begin - keywrap_core_ctrl_new = CTRL_MKM_WR_END; + mkm_init_op = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_WR_WAIT0; keywrap_core_ctrl_we = 1'h1; end + CTRL_MKM_WR_WAIT0: + begin + if (mkm_ready) + begin + keywrap_core_ctrl_new = CTRL_MKM_WR_END; + keywrap_core_ctrl_we = 1'h1; + end + end + + CTRL_MKM_WR_END: begin ready_new = 1'h1; diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v index 4b94b26..27a2e91 100644 --- a/src/tb/tb_keywrap_core.v +++ b/src/tb/tb_keywrap_core.v @@ -67,11 +67,15 @@ module tb_keywrap_core(); reg tb_read; reg tb_write; reg tb_encdec; + reg tb_mkey_mstatus; wire tb_ready; wire tb_valid; reg [(RLEN_BITS - 1) : 0] tb_rlen; reg [255 : 0] tb_key; + reg [31 : 0] tb_status; reg tb_keylen; + wire [255 : 0] tb_mkey; + wire [31 : 0] tb_mstatus; reg [63 : 0] tb_a_init; wire [63 : 0] tb_a_result; reg tb_api_we; @@ -102,7 +106,8 @@ module tb_keywrap_core(); .next(tb_next), .read(tb_read), .write(tb_write), - .encdec(tb_encdec), + .mkey_mstatus(tb_mkey_mstatus), + .encdec(tb_encdec), .ready(tb_ready), .valid(tb_valid), @@ -110,6 +115,9 @@ module tb_keywrap_core(); .rlen(tb_rlen), .key(tb_key), .keylen(tb_keylen), + .status(tb_status), + .mkey(tb_mkey), + .mstatus(tb_mstatus), .a_init(tb_a_init), .a_result(tb_a_result), @@ -161,18 +169,20 @@ module tb_keywrap_core(); tb_clk = 0; tb_reset_n = 0; - tb_init = 0; - tb_next = 0; - tb_read = 0; - tb_write = 0; - tb_encdec = 0; - tb_rlen = 13'h0; - tb_key = 256'h0; - tb_keylen = 0; - tb_a_init = 64'h0; - tb_api_we = 0; - tb_api_addr = 14'h0; - tb_api_wr_data = 32'h0; + tb_init = 0; + tb_next = 0; + tb_read = 0; + tb_write = 0; + tb_encdec = 0; + tb_mkey_mstatus = 0; + tb_rlen = 13'h0; + tb_key = 256'h0; + tb_status = 32'h0; + tb_keylen = 0; + tb_a_init = 64'h0; + tb_api_we = 0; + tb_api_addr = 14'h0; + tb_api_wr_data = 32'h0; #(CLK_PERIOD * 10); -- cgit v1.2.3 From 491a5db2c4379af748499691f173874aed19de22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 10:24:53 +0200 Subject: Adding initial version of mkmif wrapper used by keywrap_core to hide protocol complexity. --- src/rtl/keywrap_mkmif.v | 258 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 258 insertions(+) create mode 100644 src/rtl/keywrap_mkmif.v diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v new file mode 100644 index 0000000..bb08921 --- /dev/null +++ b/src/rtl/keywrap_mkmif.v @@ -0,0 +1,258 @@ +//====================================================================== +// +// keywrap_mkmif.v +// --------------- +// Wrapper for the mkmif_core. This allow us to simplify the +// integration of the mkmif in keywrap_core. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2018, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module keywrap_mkmif ( + input wire clk, + input wire reset_n, + + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + + input wire init, + input wire read, + input wire write, + input wire key_status, + output wire ready, + + input wire [31 : 0] wr_status, + output wire [31 : 0] rd_status, + input wire [255 : 0] wr_key, + output wire [255 : 0] rd_key + ); + + + //---------------------------------------------------------------- + // Paramenters and local defines. + //---------------------------------------------------------------- + localparam CTRL_IDLE = 4'h0; + localparam CTRL_INIT_WAIT = 4'h1; + localparam CTRL_NEXT_WSTART = 4'h2; + localparam CTRL_NEXT_USTART = 4'h3; + localparam CTRL_NEXT_LOOP0 = 4'h4; + localparam CTRL_NEXT_LOOP = 4'h5; + localparam CTRL_NEXT_WAIT = 4'h6; + localparam CTRL_NEXT_UPDATE = 4'h7; + localparam CTRL_NEXT_WCHECK = 4'h8; + localparam CTRL_NEXT_UCHECK = 4'h9; + localparam CTRL_NEXT_FINALIZE = 4'ha; + + // Addresses for storage in the mkm + localparam MKM_STATUS_WORD = 16'h00; + localparam MKM_KEY_BASE_WORD = 16'h04; + + localparam DEFAULT_SCLK_DIV = 16'h0020; + + + //---------------------------------------------------------------- + // Registers and memories including control signals. + //---------------------------------------------------------------- + reg [31 : 0] key_reg [0 : 7]; + reg key_we; + + reg [2 : 0] key_word_ctr_reg; + reg [2 : 0] key_word_ctr_new; + reg key_word_ctr_we; + reg key_word_ctr_rst; + reg key_word_ctr_inc; + + reg [31 : 0] status_reg; + reg [31 : 0] status_new; + reg status_we; + + reg ready_reg; + reg ready_new; + reg ready_we; + + reg [3 : 0] keywrap_mkmif_ctrl_reg; + reg [3 : 0] keywrap_mkmif_ctrl_new; + reg keywrap_mkmif_ctrl_we; + + + //---------------------------------------------------------------- + // Wires. + //---------------------------------------------------------------- + reg mkm_init_op; + reg mkm_read_op; + reg mkm_write_op; + wire mkm_ready; + wire mkm_valid; + reg [15 : 0] mkm_sclk_div; + reg [15 : 0] mkm_addr; + reg [31 : 0] mkm_write_data; + wire [31 : 0] mkm_read_data; + + + //---------------------------------------------------------------- + // Instantiations. + //---------------------------------------------------------------- + mkmif_core mkm( + .clk(clk), + .reset_n(reset_n), + + .spi_sclk(mkm_spi_sclk), + .spi_cs_n(mkm_spi_cs_n), + .spi_do(mkm_spi_do), + .spi_di(mkm_spi_di), + + .init_op(mkm_init_op), + .read_op(mkm_read_op), + .write_op(mkm_write_op), + + .ready(mkm_ready), + .valid(mkm_valid), + + .sclk_div(mkm_sclk_div), + .addr(mkm_addr), + .write_data(mkm_write_data), + .read_data(mkm_read_data) + ); + + + //---------------------------------------------------------------- + // Assignments for ports. + //---------------------------------------------------------------- + + + //---------------------------------------------------------------- + // reg_update + //---------------------------------------------------------------- + always @ (posedge clk or negedge reset_n) + begin: reg_update + integer i; + + if (!reset_n) + begin + for (i = 0 ; i < 8 ; i = i + 1) + key[i] <= 32'h0; + + ready_reg <= 1'h1; + status_reg <= 32'h0; + key_word_ctr_reg <= 3'h0; + keywrap_mkmif_ctrl_reg <= CTRL_IDLE; + end + + else + begin + if (ready_we) + ready_reg <= ready_new; + + if (key_we) + key_reg[key_word_ctr_reg] <= mkm_read_data; + + if (status_we) + status_reg <= mkm_read_data; + + if (key_word_ctr_we) + key_word_ctr_reg <= key_word_ctr_new; + + if (keywrap_mkmif_ctrl_we) + keywrap_mkmif_ctrl_reg <= keywrap_mkmif_ctrl_new; + end + end // reg_update + + + //---------------------------------------------------------------- + // key_word_ctr + //---------------------------------------------------------------- + always @* + begin : key_word_ctr + key_word_ctr_new = 3'h0; + key_word_ctr_we = 1'h0; + + if (key_word_ctr_rst) + begin + iteration_ctr_new = 3'h0; + iteration_ctr_we = 1'h1; + end + + if (key_word_ctr_inc) + begin + key_word_ctr_new = key_word_ctr_reg + 1'h1; + key_word_ctr_we = 1'h1; + end + + end + + + //---------------------------------------------------------------- + // keywrap_mkmif_ctrl + //---------------------------------------------------------------- + always @* + begin : keywrap_mkmif_ctrl + ready_new = 1'h0; + ready_we = 1'h0; + key_we = 1'h0; + key_word_ctr_rst = 1'h0; + key_word_ctr_inc = 1'h0; + status_we = 1'h0; + mkm_init_op = 1'h0; + mkm_read_op = 1'h0; + mkm_write_op = 1'h0; + mkm_sclk_div = DEFAULT_SCLK_DIV; + mkm_addr = 16'h0; + mkm_write_data = 32'h0; + + keywrap_mkmif_ctrl_new = CTRL_IDLE; + keywrap_mkmif_ctrl_we = 1'h0; + + case (keywrap_mkmif_ctrl_reg) + CTRL_IDLE: + begin + if (init) + begin + ready_new = 1'h0; + ready_we = 1'h1; + end + end + + default: + begin + + end + endcase // case (keywrap_mkmif_ctrl_reg) + end // keywrap_mkmif_ctrl + +endmodule // keywrap_mkmif + +//====================================================================== +// EOF keywrap_mkmif.v +//====================================================================== -- cgit v1.2.3 From 86d87571a957365be5191cce7503c8c66c41557e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 11:47:27 +0200 Subject: Got all states needed. Added hold registers for address and data to be written. --- src/rtl/keywrap_mkmif.v | 191 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 169 insertions(+), 22 deletions(-) diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index bb08921..72eaaf4 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -76,10 +76,10 @@ module keywrap_mkmif ( localparam CTRL_NEXT_FINALIZE = 4'ha; // Addresses for storage in the mkm - localparam MKM_STATUS_WORD = 16'h00; - localparam MKM_KEY_BASE_WORD = 16'h04; + localparam MKM_STATUS_WORD = 16'h00; + localparam MKM_KEY_BASE_WORD = 16'h04; - localparam DEFAULT_SCLK_DIV = 16'h0020; + localparam DEFAULT_SCLK_DIV = 16'h0020; //---------------------------------------------------------------- @@ -94,6 +94,14 @@ module keywrap_mkmif ( reg key_word_ctr_rst; reg key_word_ctr_inc; + reg [15 : 0] mkm_addr_reg; + reg [15 : 0] mkm_addr_new; + reg mkm_addr_we; + + reg [31 : 0] mkm_write_data_reg; + reg [31 : 0] mkm_write_data_new; + reg mkm_write_data_we; + reg [31 : 0] status_reg; reg [31 : 0] status_new; reg status_we; @@ -115,7 +123,6 @@ module keywrap_mkmif ( reg mkm_write_op; wire mkm_ready; wire mkm_valid; - reg [15 : 0] mkm_sclk_div; reg [15 : 0] mkm_addr; reg [31 : 0] mkm_write_data; wire [31 : 0] mkm_read_data; @@ -140,9 +147,9 @@ module keywrap_mkmif ( .ready(mkm_ready), .valid(mkm_valid), - .sclk_div(mkm_sclk_div), - .addr(mkm_addr), - .write_data(mkm_write_data), + .sclk_div(DEFAULT_SCLK_DIV), + .addr(mkm_addr_reg), + .write_data(mkm_write_data_reg), .read_data(mkm_read_data) ); @@ -150,6 +157,12 @@ module keywrap_mkmif ( //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- + assign ready = ready_reg; + + assign rd_status = status_reg; + + assign rd_key = {key_reg[7], key_reg[6], key_reg[5], key_reg[4], + key_reg[3], key_reg[2], key_reg[1], key_reg[0]}; //---------------------------------------------------------------- @@ -166,6 +179,8 @@ module keywrap_mkmif ( ready_reg <= 1'h1; status_reg <= 32'h0; + mkm_address_reg <= 16'h0; + mkm_write_data_reg <= 32'h0; key_word_ctr_reg <= 3'h0; keywrap_mkmif_ctrl_reg <= CTRL_IDLE; end @@ -175,6 +190,12 @@ module keywrap_mkmif ( if (ready_we) ready_reg <= ready_new; + if (mkm_addr_we) + mkm_addr_reg <= mkm_addr_new; + + if (mkm_write_data_we) + mkm_write_data_reg <= mkm_write_data_new; + if (key_we) key_reg[key_word_ctr_reg] <= mkm_read_data; @@ -218,19 +239,20 @@ module keywrap_mkmif ( //---------------------------------------------------------------- always @* begin : keywrap_mkmif_ctrl - ready_new = 1'h0; - ready_we = 1'h0; - key_we = 1'h0; - key_word_ctr_rst = 1'h0; - key_word_ctr_inc = 1'h0; - status_we = 1'h0; - mkm_init_op = 1'h0; - mkm_read_op = 1'h0; - mkm_write_op = 1'h0; - mkm_sclk_div = DEFAULT_SCLK_DIV; - mkm_addr = 16'h0; - mkm_write_data = 32'h0; - + ready_new = 1'h0; + ready_we = 1'h0; + key_we = 1'h0; + key_word_ctr_rst = 1'h0; + key_word_ctr_inc = 1'h0; + status_we = 1'h0; + mkm_init_op = 1'h0; + mkm_read_op = 1'h0; + mkm_write_op = 1'h0; + mkm_sclk_div = DEFAULT_SCLK_DIV; + mkm_addr_new = 16'h0; + mkm_addr_we = 1'h0; + mkm_write_data_new = 32'h0; + mkm_write_data_we = 1'h0; keywrap_mkmif_ctrl_new = CTRL_IDLE; keywrap_mkmif_ctrl_we = 1'h0; @@ -239,8 +261,133 @@ module keywrap_mkmif ( begin if (init) begin - ready_new = 1'h0; - ready_we = 1'h1; + mkm_init_op = 1'h1; + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + + if (read) + begin + ready_new = 1'h0; + ready_we = 1'h1; + + if (key_status) + begin + key_word_ctr_rst = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_READ_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + mkm_read_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD; + mkm_addr_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_READ_STATUS_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + + if (write) + if (key_status) + begin + key_word_ctr_rst = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + mkm_write_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD; + mkm_addr_we = 1'h1; + mkm_write_data_new = wr_status; + mkm_write_data_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + end + + CTRL_WAIT: + begin + if (mkm_ready) + begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_IDLE; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + CTRL_READ_STATUS_WAIT: + begin + if (mkm_ready) + begin + status_we = 1'h1; + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_IDLE; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + CTRL_READ_KEY: + if (key_word_ctr_reg < 8) + begin + mkm_read_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0}; + mkm_addr_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_IDLE; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + CTRL_READ_KEY_WAIT: + begin + if (mkm_ready) + begin + key_we = 1'h1; + key_word_ctr_inc = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_READ_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + CTRL_WRITE_KEY: + begin + if (key_word_ctr_reg < 8) + begin + mkm_write_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0}; + mkm_addr_we = 1'h1; + mkm_write_data_new = key; + mkm_write_data_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_IDLE; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + CTRL_WRITE_KEY_WAIT: + begin + if (mkm_ready) + begin + key_word_ctr_inc = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; + keywrap_mkmif_ctrl_we = 1'h1; end end -- cgit v1.2.3 From d832fcd65677d54b23dce2f08fd7208c21e50564 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 12:21:10 +0200 Subject: Completed the functionality that should be in the wrapper. Now its just debugging... --- src/rtl/keywrap_mkmif.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index 72eaaf4..31b7c09 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -367,7 +367,7 @@ module keywrap_mkmif ( mkm_write_op = 1'h1; mkm_addr_new = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0}; mkm_addr_we = 1'h1; - mkm_write_data_new = key; + mkm_write_data_new = key[key_word_ctr_reg * 32 +: 32]; mkm_write_data_we = 1'h1; keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY_WAIT; keywrap_mkmif_ctrl_we = 1'h1; -- cgit v1.2.3 From 9619025dff8a3a28dea0bc9379f8e33cea1c48dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 12:23:07 +0200 Subject: Some whitespace cleanup. --- src/rtl/keywrap_mkmif.v | 52 ++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index 31b7c09..0399a04 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -39,24 +39,24 @@ //====================================================================== module keywrap_mkmif ( - input wire clk, - input wire reset_n, - - output wire mkm_spi_sclk, - output wire mkm_spi_cs_n, - input wire mkm_spi_do, - output wire mkm_spi_di, - - input wire init, - input wire read, - input wire write, - input wire key_status, - output wire ready, - - input wire [31 : 0] wr_status, - output wire [31 : 0] rd_status, - input wire [255 : 0] wr_key, - output wire [255 : 0] rd_key + input wire clk, + input wire reset_n, + + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + + input wire init, + input wire read, + input wire write, + input wire key_status, + output wire ready, + + input wire [31 : 0] wr_status, + output wire [31 : 0] rd_status, + input wire [255 : 0] wr_key, + output wire [255 : 0] rd_key ); @@ -118,14 +118,14 @@ module keywrap_mkmif ( //---------------------------------------------------------------- // Wires. //---------------------------------------------------------------- - reg mkm_init_op; - reg mkm_read_op; - reg mkm_write_op; - wire mkm_ready; - wire mkm_valid; - reg [15 : 0] mkm_addr; - reg [31 : 0] mkm_write_data; - wire [31 : 0] mkm_read_data; + reg mkm_init_op; + reg mkm_read_op; + reg mkm_write_op; + wire mkm_ready; + wire mkm_valid; + reg [15 : 0] mkm_addr; + reg [31 : 0] mkm_write_data; + wire [31 : 0] mkm_read_data; //---------------------------------------------------------------- -- cgit v1.2.3 From 4da2caadb9219e5126ef15ec133faa36e61049c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 12:37:04 +0200 Subject: Integrated new mkmif_core wrapper. --- src/rtl/keywrap_core.v | 71 +++++++++++++++++-------------------------------- src/rtl/keywrap_mkmif.v | 22 +++++++-------- toolruns/Makefile | 4 +-- 3 files changed, 35 insertions(+), 62 deletions(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 00e8391..533cc83 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -153,21 +153,6 @@ module keywrap_core #(parameter MEM_BITS = 11) reg iteration_ctr_set; reg iteration_ctr_rst; - reg [31 : 0] mkm_key [0 : 7]; - reg mkm_key_we; - - reg [2 : 0] mkm_word_ctr_reg; - reg [2 : 0] mkm_word_ctr_new; - reg mkm_word_ctr_we; - - reg [7 : 0] mkm_addr_reg; - reg [7 : 0] mkm_addr_new; - reg mkm_addr_we; - - reg [31 : 0] mkm_status_reg; - reg [31 : 0] mkm_status_new; - reg mkm_status_we; - reg [5 : 0] keywrap_core_ctrl_reg; reg [5 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; @@ -190,15 +175,14 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; - reg mkm_init_op; - reg mkm_read_op; - reg mkm_write_op; + reg mkm_init; + reg mkm_read; + reg mkm_write; + reg mkm_key_status; wire mkm_ready; - wire mkm_valid; - reg [15 : 0] mkm_sclk_div; - reg [15 : 0] mkm_addr; - reg [31 : 0] mkm_write_data; - wire [31 : 0] mkm_read_data; + wire [255 : 0] mkm_key; + wire [31 : 0] mkm_rd_status; + wire [31 : 0] mkm_wr_status; //---------------------------------------------------------------- @@ -239,27 +223,26 @@ module keywrap_core #(parameter MEM_BITS = 11) ); - mkmif_core mkm( - .clk(clk), - .reset_n(reset_n), - - .spi_sclk(mkm_spi_sclk), - .spi_cs_n(mkm_spi_cs_n), - .spi_do(mkm_spi_do), - .spi_di(mkm_spi_di), + keywrap_mkmif mkmif( + .clk(clk), + .reset_n(reset_n), - .init_op(mkm_init_op), - .read_op(mkm_read_op), - .write_op(mkm_write_op), + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), - .ready(mkm_ready), - .valid(mkm_valid), + .init(mkm_init), + .read(mkm_read), + .write(mkm_write), + .key_status(mkm_key_status), + .ready(mkm_ready), - .sclk_div(mkm_sclk_div), - .addr(mkm_addr), - .write_data(mkm_write_data), - .read_data(mkm_read_data) - ); + .wr_status(mkm_wr_status), + .rd_status(mkm_rd_status), + .wr_key(key), + .rd_key(mkm_key) + ); //---------------------------------------------------------------- @@ -280,17 +263,11 @@ module keywrap_core #(parameter MEM_BITS = 11) if (!reset_n) begin - for (i = 0 ; i < 8 ; i = i + 1) - mkm_key[i] <= 32'h0; - a_reg <= 64'h0; ready_reg <= 1'h1; valid_reg <= 1'h1; block_ctr_reg <= {(MEM_BITS - 1){1'h0}}; iteration_ctr_reg <= 3'h0; - mkm_word_ctr_reg <= 3'h0; - mkm_addr_reg <= 8'h0; - mkm_status_reg <= 32'h0; keywrap_core_ctrl_reg <= CTRL_IDLE; end diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index 0399a04..082173b 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -63,17 +63,13 @@ module keywrap_mkmif ( //---------------------------------------------------------------- // Paramenters and local defines. //---------------------------------------------------------------- - localparam CTRL_IDLE = 4'h0; - localparam CTRL_INIT_WAIT = 4'h1; - localparam CTRL_NEXT_WSTART = 4'h2; - localparam CTRL_NEXT_USTART = 4'h3; - localparam CTRL_NEXT_LOOP0 = 4'h4; - localparam CTRL_NEXT_LOOP = 4'h5; - localparam CTRL_NEXT_WAIT = 4'h6; - localparam CTRL_NEXT_UPDATE = 4'h7; - localparam CTRL_NEXT_WCHECK = 4'h8; - localparam CTRL_NEXT_UCHECK = 4'h9; - localparam CTRL_NEXT_FINALIZE = 4'ha; + localparam CTRL_IDLE = 3'h0; + localparam CTRL_WAIT = 3'h1; + localparam CTRL_READ_STATUS_WAIT = 3'h2; + localparam CTRL_READ_KEY = 3'h3; + localparam CTRL_READ_KEY_WAIT = 3'h4; + localparam CTRL_WRITE_KEY = 3'h5; + localparam CTRL_WRITE_KEY_WAIT = 3'h6; // Addresses for storage in the mkm localparam MKM_STATUS_WORD = 16'h00; @@ -110,8 +106,8 @@ module keywrap_mkmif ( reg ready_new; reg ready_we; - reg [3 : 0] keywrap_mkmif_ctrl_reg; - reg [3 : 0] keywrap_mkmif_ctrl_new; + reg [2 : 0] keywrap_mkmif_ctrl_reg; + reg [2 : 0] keywrap_mkmif_ctrl_new; reg keywrap_mkmif_ctrl_we; diff --git a/toolruns/Makefile b/toolruns/Makefile index 3ea00bd..4ca1d54 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -38,7 +38,7 @@ #=================================================================== MKMIF_PATH = ../../mkmif/src/rtl -MKMIF_SRC = $(MKMIF_PATH)/mkmif.v $(MKMIF_PATH)/mkmif_core.v $(MKMIF_PATH)/mkmif_spi.v +MKMIF_SRC = $(MKMIF_PATH)/mkmif_core.v $(MKMIF_PATH)/mkmif_spi.v AES_PATH = ../../../../core/cipher/aes_speed/src/rtl AES_SRC = $(AES_PATH)/aes_core.v $(AES_PATH)/aes_decipher_block.v $(AES_PATH)/aes_encipher_block.v $(AES_PATH)/aes_inv_sbox.v $(AES_PATH)/aes_key_mem.v $(AES_PATH)/aes_sbox.v @@ -46,7 +46,7 @@ AES_SRC = $(AES_PATH)/aes_core.v $(AES_PATH)/aes_decipher_block.v $(AES_PATH)/ae MEM_SRC = ../src/rtl/keywrap_mem.v TB_MEM_SRC = ../src/tb/tb_keywrap_mem.v -CORE_SRC = ../src/rtl/keywrap_core.v $(AES_SRC) $(MEM_SRC) $(MKMIF_SRC) +CORE_SRC = ../src/rtl/keywrap_core.v ../src/rtl/keywrap_mkmif.v $(AES_SRC) $(MEM_SRC) $(MKMIF_SRC) TB_CORE_SRC = ../src/tb/tb_keywrap_core.v TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) -- cgit v1.2.3 From d4bd0c2e50acafb94dc6e37581ed83d7c30bf46a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 13:37:06 +0200 Subject: Completed syntax debug after integration of new mkmif_core wrapper. --- src/rtl/keywrap_core.v | 184 +++++++++++++++-------------------------------- src/rtl/keywrap_mkmif.v | 12 ++-- src/tb/tb_keywrap_core.v | 3 + 3 files changed, 66 insertions(+), 133 deletions(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index 533cc83..cf6e00a 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -55,6 +55,7 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire read, input wire write, input wire mkey_mstatus, + input wire mkey_key, input wire encdec, output wire ready, @@ -82,43 +83,19 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- localparam MAX_ITERATIONS = 6 - 1; - localparam CTRL_IDLE = 6'h0; - localparam CTRL_INIT_WAIT = 6'h1; - localparam CTRL_NEXT_WSTART = 6'h2; - localparam CTRL_NEXT_USTART = 6'h3; - localparam CTRL_NEXT_LOOP0 = 6'h4; - localparam CTRL_NEXT_LOOP = 6'h5; - localparam CTRL_NEXT_WAIT = 6'h6; - localparam CTRL_NEXT_UPDATE = 6'h7; - localparam CTRL_NEXT_WCHECK = 6'h8; - localparam CTRL_NEXT_UCHECK = 6'h9; - localparam CTRL_NEXT_FINALIZE = 6'ha; - - localparam CTRL_MKM_RD_START = 6'h10; - localparam CTRL_MKM_RD_WAIT0 = 6'h11; - localparam CTRL_MKM_RD_STATUS = 6'h12; - localparam CTRL_MKM_RD_END = 6'h13; - - localparam CTRL_MKM_WR_START = 6'h18; - localparam CTRL_MKM_WR_WAIT0 = 6'h19; - localparam CTRL_MKM_WR_END = 6'h1a; - - // API for mkm used by the core. - localparam MKM_ADDR_CTRL = 8'h08; - localparam MKM_CTRL_READ_BIT = 0; - localparam MKM_CTRL_WRITE_BIT = 1; - localparam MKM_ADDR_STATUS = 8'h09; - localparam MKM_STATUS_READY_BIT = 0; - localparam MKM_STATUS_VALID_BIT = 1; - localparam MKM_ADDR_SCLK_DIV = 8'h0a; - localparam MKM_ADDR_EMEM_ADDR = 8'h10; - localparam MKM_ADDR_EMEM_DATA = 8'h20; - - // Addresses for storage in the mkm - localparam MKM_STATUS_WORD = 16'h00; - localparam MKM_KEY_BASE_WORD = 16'h04; - - localparam DEFAULT_SCLK_DIV = 16'h0020; + localparam CTRL_RESET = 4'h0; + localparam CTRL_IDLE = 4'h1; + localparam CTRL_INIT_WAIT = 4'h2; + localparam CTRL_NEXT_WSTART = 4'h3; + localparam CTRL_NEXT_USTART = 4'h4; + localparam CTRL_NEXT_LOOP0 = 4'h5; + localparam CTRL_NEXT_LOOP = 4'h6; + localparam CTRL_NEXT_WAIT = 4'h7; + localparam CTRL_NEXT_UPDATE = 4'h8; + localparam CTRL_NEXT_WCHECK = 4'h9; + localparam CTRL_NEXT_UCHECK = 4'ha; + localparam CTRL_NEXT_FINALIZE = 4'hb; + localparam CTRL_MKM_WAIT = 4'hc; //---------------------------------------------------------------- @@ -153,8 +130,8 @@ module keywrap_core #(parameter MEM_BITS = 11) reg iteration_ctr_set; reg iteration_ctr_rst; - reg [5 : 0] keywrap_core_ctrl_reg; - reg [5 : 0] keywrap_core_ctrl_new; + reg [3 : 0] keywrap_core_ctrl_reg; + reg [3 : 0] keywrap_core_ctrl_new; reg keywrap_core_ctrl_we; @@ -167,6 +144,7 @@ module keywrap_core #(parameter MEM_BITS = 11) wire aes_valid; reg [127 : 0] aes_block; wire [127 : 0] aes_result; + reg [255 : 0] aes_key; reg update_state; @@ -180,7 +158,7 @@ module keywrap_core #(parameter MEM_BITS = 11) reg mkm_write; reg mkm_key_status; wire mkm_ready; - wire [255 : 0] mkm_key; + wire [255 : 0] mkm_rd_key; wire [31 : 0] mkm_rd_status; wire [31 : 0] mkm_wr_status; @@ -212,7 +190,7 @@ module keywrap_core #(parameter MEM_BITS = 11) .init(aes_init), .next(aes_next), - .key(key), + .key(aes_key), .keylen(keylen), .block(aes_block), @@ -235,13 +213,13 @@ module keywrap_core #(parameter MEM_BITS = 11) .init(mkm_init), .read(mkm_read), .write(mkm_write), - .key_status(mkm_key_status), + .key_status(mkey_mstatus), .ready(mkm_ready), .wr_status(mkm_wr_status), .rd_status(mkm_rd_status), .wr_key(key), - .rd_key(mkm_key) + .rd_key(mkm_rd_key) ); @@ -251,7 +229,8 @@ module keywrap_core #(parameter MEM_BITS = 11) assign a_result = a_reg; assign ready = ready_reg; assign valid = valid_reg; - assign mstatus = mkm_status_reg; + assign mkey = mkm_rd_key; + assign mstatus = mkm_rd_status; //---------------------------------------------------------------- @@ -268,7 +247,7 @@ module keywrap_core #(parameter MEM_BITS = 11) valid_reg <= 1'h1; block_ctr_reg <= {(MEM_BITS - 1){1'h0}}; iteration_ctr_reg <= 3'h0; - keywrap_core_ctrl_reg <= CTRL_IDLE; + keywrap_core_ctrl_reg <= CTRL_RESET; end else @@ -276,9 +255,6 @@ module keywrap_core #(parameter MEM_BITS = 11) if (a_we) a_reg <= a_new; - if (mkm_status_we) - mkm_status_reg <= mkm_read_data; - if (ready_we) ready_reg <= ready_new; @@ -407,6 +383,17 @@ module keywrap_core #(parameter MEM_BITS = 11) end + //---------------------------------------------------------------- + // aes_key_mux + //---------------------------------------------------------------- + always @* + begin + if (mkey_key) + aes_key = mkm_rd_key; + else + aes_key = key; + end + //---------------------------------------------------------------- // keywrap_core_ctrl @@ -421,6 +408,9 @@ module keywrap_core #(parameter MEM_BITS = 11) update_state = 1'h0; aes_init = 1'h0; aes_next = 1'h0; + mkm_init = 1'h0; + mkm_read = 1'h0; + mkm_write = 1'h0; block_ctr_dec = 1'h0; block_ctr_inc = 1'h0; block_ctr_rst = 1'h0; @@ -430,18 +420,21 @@ module keywrap_core #(parameter MEM_BITS = 11) iteration_ctr_set = 1'h0; iteration_ctr_rst = 1'h0; - mkm_init_op = 1'h0; - mkm_read_op = 1'h0; - mkm_write_op = 1'h0; - mkm_sclk_div = DEFAULT_SCLK_DIV; - mkm_addr = 16'h0; - mkm_write_data = 32'h0; - keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h0; case (keywrap_core_ctrl_reg) + CTRL_RESET: + begin + mkm_init = 1'h1; + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_WAIT; + keywrap_core_ctrl_we = 1'h0; + end + + CTRL_IDLE: begin if (init) @@ -472,17 +465,20 @@ module keywrap_core #(parameter MEM_BITS = 11) if (read) begin + mkm_write = 1'h1; ready_new = 1'h0; ready_we = 1'h1; - keywrap_core_ctrl_new = CTRL_MKM_RD_START; + mkm_read = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_WAIT; keywrap_core_ctrl_we = 1'h1; end if (write) begin + mkm_write = 1'h1; ready_new = 1'h0; ready_we = 1'h1; - keywrap_core_ctrl_new = CTRL_MKM_WR_START; + keywrap_core_ctrl_new = CTRL_MKM_WAIT; keywrap_core_ctrl_we = 1'h1; end end @@ -616,85 +612,19 @@ module keywrap_core #(parameter MEM_BITS = 11) end - CTRL_MKM_RD_START: - begin - mkm_init_op = 1'h1; - keywrap_core_ctrl_new = CTRL_MKM_RD_WAIT0; - keywrap_core_ctrl_we = 1'h1; - end - - - CTRL_MKM_RD_WAIT0: - begin - if (mkm_ready) - // MKM should have been initialized. - if (mkey_mstatus) - begin - // Read master key from mkm. - keywrap_core_ctrl_new = CTRL_MKM_RD_END; - keywrap_core_ctrl_we = 1'h1; - end - else - begin - // Read master key status from mkm. - mkm_read_op = 1'h1; - mkm_addr = MKM_STATUS_WORD; - keywrap_core_ctrl_new = CTRL_MKM_RD_STATUS; - keywrap_core_ctrl_we = 1'h1; - end - end - - - CTRL_MKM_RD_STATUS: - begin - if (mkm_ready) - begin - // status should have been read. - mkm_status_we = 1'h1; - keywrap_core_ctrl_new = CTRL_MKM_RD_END; - keywrap_core_ctrl_we = 1'h1; - end - end - - - CTRL_MKM_RD_END: - begin - ready_new = 1'h1; - ready_we = 1'h1; - keywrap_core_ctrl_new = CTRL_IDLE; - keywrap_core_ctrl_we = 1'h1; - end - - - CTRL_MKM_WR_START: - begin - mkm_init_op = 1'h1; - keywrap_core_ctrl_new = CTRL_MKM_WR_WAIT0; - keywrap_core_ctrl_we = 1'h1; - end - - - CTRL_MKM_WR_WAIT0: + CTRL_MKM_WAIT: begin if (mkm_ready) begin - keywrap_core_ctrl_new = CTRL_MKM_WR_END; + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h1; end end - - CTRL_MKM_WR_END: - begin - ready_new = 1'h1; - ready_we = 1'h1; - keywrap_core_ctrl_new = CTRL_IDLE; - keywrap_core_ctrl_we = 1'h1; - end - default: begin - end endcase // case (keywrap_core_ctrl_reg) end // keywrap_core_ctrl diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index 082173b..ad2121e 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -171,11 +171,11 @@ module keywrap_mkmif ( if (!reset_n) begin for (i = 0 ; i < 8 ; i = i + 1) - key[i] <= 32'h0; + key_reg[i] <= 32'h0; ready_reg <= 1'h1; status_reg <= 32'h0; - mkm_address_reg <= 16'h0; + mkm_addr_reg <= 16'h0; mkm_write_data_reg <= 32'h0; key_word_ctr_reg <= 3'h0; keywrap_mkmif_ctrl_reg <= CTRL_IDLE; @@ -217,8 +217,8 @@ module keywrap_mkmif ( if (key_word_ctr_rst) begin - iteration_ctr_new = 3'h0; - iteration_ctr_we = 1'h1; + key_word_ctr_new = 3'h0; + key_word_ctr_we = 1'h1; end if (key_word_ctr_inc) @@ -244,7 +244,6 @@ module keywrap_mkmif ( mkm_init_op = 1'h0; mkm_read_op = 1'h0; mkm_write_op = 1'h0; - mkm_sclk_div = DEFAULT_SCLK_DIV; mkm_addr_new = 16'h0; mkm_addr_we = 1'h0; mkm_write_data_new = 32'h0; @@ -328,6 +327,7 @@ module keywrap_mkmif ( end CTRL_READ_KEY: + begin if (key_word_ctr_reg < 8) begin mkm_read_op = 1'h1; @@ -363,7 +363,7 @@ module keywrap_mkmif ( mkm_write_op = 1'h1; mkm_addr_new = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0}; mkm_addr_we = 1'h1; - mkm_write_data_new = key[key_word_ctr_reg * 32 +: 32]; + mkm_write_data_new = wr_key[key_word_ctr_reg * 32 +: 32]; mkm_write_data_we = 1'h1; keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY_WAIT; keywrap_mkmif_ctrl_we = 1'h1; diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v index 27a2e91..07777aa 100644 --- a/src/tb/tb_keywrap_core.v +++ b/src/tb/tb_keywrap_core.v @@ -68,6 +68,7 @@ module tb_keywrap_core(); reg tb_write; reg tb_encdec; reg tb_mkey_mstatus; + reg tb_mkey_key; wire tb_ready; wire tb_valid; reg [(RLEN_BITS - 1) : 0] tb_rlen; @@ -107,6 +108,7 @@ module tb_keywrap_core(); .read(tb_read), .write(tb_write), .mkey_mstatus(tb_mkey_mstatus), + .mkey_key(tb_mkey_key), .encdec(tb_encdec), .ready(tb_ready), @@ -175,6 +177,7 @@ module tb_keywrap_core(); tb_write = 0; tb_encdec = 0; tb_mkey_mstatus = 0; + tb_mkey_key = 0; tb_rlen = 13'h0; tb_key = 256'h0; tb_status = 32'h0; -- cgit v1.2.3 From 4e1cb1dbf22b93bde1cf3d5214e47f22d3d21cdc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 28 Sep 2018 15:47:15 +0200 Subject: Adding initial version of testbench for the mkmif wrapper. --- src/tb/tb_keywrap_mkmif.v | 153 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 src/tb/tb_keywrap_mkmif.v diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v new file mode 100644 index 0000000..09fe652 --- /dev/null +++ b/src/tb/tb_keywrap_mkmif.v @@ -0,0 +1,153 @@ +//====================================================================== +// +// tb_keywrap_mkm.v +// ---------------- +// Testbench for the mkmif wrapper in keywrap. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2018, NORDUnet A/S +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module tb_keywrap_mkm(); + + //---------------------------------------------------------------- + // Parameters. + //---------------------------------------------------------------- + parameter DEBUG = 1; + + parameter CLK_HALF_PERIOD = 1; + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + + //---------------------------------------------------------------- + // Variables, regs and wires. + //---------------------------------------------------------------- + integer cycle_ctr; + integer error_ctr; + integer tc_ctr; + + reg tb_clk; + reg tb_reset_n; + + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + keywrap_mkmif dut( + .clk(tb_clk), + .reset_n(tb_reset_n), + + .mkm_spi_sclk(), + .mkm_spi_cs_n(), + .mkm_spi_do(), + .mkm_spi_di(), + + .init(), + .read(), + .write(), + .key_status(), + .ready(), + + .wr_status(), + .rd_status(), + .wr_key(), + .rd_key + ); + + + //---------------------------------------------------------------- + // clk_gen + // + // Always running clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #CLK_HALF_PERIOD; + tb_clk = !tb_clk; + end // clk_gen + + + //---------------------------------------------------------------- + // sys_monitor() + // + // An always running process that creates a cycle counter and + // conditionally displays information about the DUT. + //---------------------------------------------------------------- + always + begin : sys_monitor + cycle_ctr = cycle_ctr + 1; + + #(CLK_PERIOD); + end + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + cycle_ctr = 0; + error_ctr = 0; + tc_ctr = 0; + + tb_clk = 1'h0; + tb_reset_n = 1'h1 + + #(CLK_PERIOD); + end + endtask // init_sim + + + //---------------------------------------------------------------- + // main + //---------------------------------------------------------------- + initial + begin : main + $display(" -= Testbench for Keywrap mkmif wrapper started =-"); + $display(" ================================================"); + $display(""); + + init_sim(); + + $display(""); + $display("*** Keywrap mkmif wrapper testbench done. ***"); + $finish; + end // main + +endmodule // tb_keywrap_mkm + +//====================================================================== +// EOF tb_keywrap_mkm.v +//====================================================================== -- cgit v1.2.3 From aced6ee13af2d15ee0a9ccd8e681faf1519106ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 23 Oct 2018 10:50:22 +0200 Subject: Hardened the keywrap API to not allow reads or writes when the core is busy. --- src/rtl/keywrap.v | 55 +++++++++++++++++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index cc6f8ac..53deaaf 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -321,45 +321,48 @@ module keywrap #(parameter ADDR_BITS = 13) api_rd_delay_new = 32'h0; // api_mux - if (address[(ADDR_BITS - 1)]) - tmp_read_data = core_api_rd_data; - else - tmp_read_data = api_rd_delay_reg; + if (core_ready) + if (address[(ADDR_BITS - 1)]) + tmp_read_data = core_api_rd_data; + else + tmp_read_data = api_rd_delay_reg; if (cs) begin if (we) begin - // Write access - if (address == {{PAD{1'h0}}, ADDR_CTRL}) + if (core_ready) begin - init_new = write_data[CTRL_INIT_BIT]; - next_new = write_data[CTRL_NEXT_BIT]; - read_new = write_data[CTRL_READ_BIT]; - write_new = write_data[CTRL_WRITE_BIT]; - end + if (address == {{PAD{1'h0}}, ADDR_CTRL}) + begin + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + read_new = write_data[CTRL_READ_BIT]; + write_new = write_data[CTRL_WRITE_BIT]; + end - if (address == {{PAD{1'h0}}, ADDR_CONFIG}) - config_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_CONFIG}) + config_we = 1'h1; - if (address == {{PAD{1'h0}}, ADDR_RLEN}) - rlen_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_RLEN}) + rlen_we = 1'h1; - if (address == {{PAD{1'h0}}, ADDR_A0}) - a0_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_A0}) + a0_we = 1'h1; - if (address == {{PAD{1'h0}}, ADDR_A1}) - a1_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_A1}) + a1_we = 1'h1; - if (address == {{PAD{1'h0}}, ADDR_MSTATUS}) - mstatus_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_MSTATUS}) + mstatus_we = 1'h1; - if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && - (address <= {{PAD{1'h0}}, ADDR_KEY7})) - key_we = 1'h1; + if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && + (address <= {{PAD{1'h0}}, ADDR_KEY7})) + key_we = 1'h1; - if (address[(ADDR_BITS - 1)]) - core_api_we = 1'h1; + if (address[(ADDR_BITS - 1)]) + core_api_we = 1'h1; + end end // if (we) else begin -- cgit v1.2.3 From 9c66245ee6304146b107e1dd13b9b125e7609142 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 30 Oct 2018 15:13:35 +0100 Subject: Integrated the DUT into the testbench and update Makefile to build the sim target- --- src/tb/tb_keywrap_mkmif.v | 58 +++++++++++++++++++++++++++++++---------------- toolruns/Makefile | 15 ++++++++++-- 2 files changed, 52 insertions(+), 21 deletions(-) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 09fe652..8d42c6d 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -55,8 +55,21 @@ module tb_keywrap_mkm(); integer error_ctr; integer tc_ctr; - reg tb_clk; - reg tb_reset_n; + reg tb_clk; + reg tb_reset_n; + wire tb_mkm_spi_sclk; + wire tb_mkm_spi_cs_n; + reg tb_mkm_spi_do; + wire tb_mkm_spi_di; + reg tb_init; + reg tb_read; + reg tb_write; + reg tb_key_status; + wire tb_ready; + reg [31 : 0] tb_wr_status; + wire [31 : 0] tb_rd_status; + reg [255 : 0] tb_wr_key; + wire [255 : 0] tb_rd_key; //---------------------------------------------------------------- @@ -66,21 +79,21 @@ module tb_keywrap_mkm(); .clk(tb_clk), .reset_n(tb_reset_n), - .mkm_spi_sclk(), - .mkm_spi_cs_n(), - .mkm_spi_do(), - .mkm_spi_di(), - - .init(), - .read(), - .write(), - .key_status(), - .ready(), - - .wr_status(), - .rd_status(), - .wr_key(), - .rd_key + .mkm_spi_sclk(tb_mkm_spi_sclk), + .mkm_spi_cs_n(tb_mkm_spi_cs_n), + .mkm_spi_do(tb_mkm_spi_do), + .mkm_spi_di(tb_mkm_spi_di), + + .init(tb_init), + .read(tb_read), + .write(tb_write), + .key_status(tb_key_status), + .ready(tb_ready), + + .wr_status(tb_wr_status), + .rd_status(tb_rd_status), + .wr_key(tb_wr_key), + .rd_key(tb_rd_key) ); @@ -122,8 +135,15 @@ module tb_keywrap_mkm(); error_ctr = 0; tc_ctr = 0; - tb_clk = 1'h0; - tb_reset_n = 1'h1 + tb_clk = 1'h0; + tb_reset_n = 1'h1; + tb_mkm_spi_do = 1'h0; + tb_init = 1'h0; + tb_read = 1'h0; + tb_write = 1'h0; + tb_key_status = 1'h0; + tb_wr_status = 32'h0; + tb_wr_key = 256'h0; #(CLK_PERIOD); end diff --git a/toolruns/Makefile b/toolruns/Makefile index 4ca1d54..a6dcf00 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -46,7 +46,10 @@ AES_SRC = $(AES_PATH)/aes_core.v $(AES_PATH)/aes_decipher_block.v $(AES_PATH)/ae MEM_SRC = ../src/rtl/keywrap_mem.v TB_MEM_SRC = ../src/tb/tb_keywrap_mem.v -CORE_SRC = ../src/rtl/keywrap_core.v ../src/rtl/keywrap_mkmif.v $(AES_SRC) $(MEM_SRC) $(MKMIF_SRC) +KEYWRAP_MKMIF_SRC = ../src/rtl/keywrap_mkmif.v +TB_KEYWRAP_MKMIF_SRC = ../src/tb/tb_keywrap_mkmif.v + +CORE_SRC = ../src/rtl/keywrap_core.v $(KEYWRAP_MKMIF_SRC) $(AES_SRC) $(MEM_SRC) $(MKMIF_SRC) TB_CORE_SRC = ../src/tb/tb_keywrap_core.v TOP_SRC = ../src/rtl/keywrap.v $(CORE_SRC) @@ -58,7 +61,7 @@ CC_FLAGS = -Wall LINT = verilator LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME -all: top.sim core.sim mem.sim +all: top.sim core.sim mem.sim mkmif.sim top.sim: $(TB_TOP_SRC) $(TOP_SRC) @@ -73,6 +76,10 @@ mem.sim: $(TB_MEM_SRC) $(MEM_SRC) $(CC) $(CC_FLAGS) -o mem.sim $(TB_MEM_SRC) $(MEM_SRC) +mkmif.sim: $(TB_KEYWRAP_MKMIF_SRC) $(KEYWRAP_MKMIF_SRC) $(MKMIF_SRC) + $(CC) $(CC_FLAGS) -o mkmif.sim $(TB_KEYWRAP_MKMIF_SRC) $(KEYWRAP_MKMIF_SRC) $(MKMIF_SRC) + + sim-top: top.sim ./top.sim @@ -85,6 +92,10 @@ sim-mem: mem.sim ./mem.sim +sim-mkmif: mkmif.sim + ./mkmif.sim + + lint: $(TOP_SRC) $(LINT) $(LINT_FLAGS) $(TOP_SRC) -- cgit v1.2.3 From 74efb3cd734209511d50b43cf22b8dd77364bc24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 6 Nov 2018 14:16:01 +0100 Subject: Adding test case to observe auto-load of key and status after reset. --- src/tb/tb_keywrap_mkmif.v | 49 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 8d42c6d..8bd3a05 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -55,6 +55,8 @@ module tb_keywrap_mkm(); integer error_ctr; integer tc_ctr; + integer show_spi; + reg tb_clk; reg tb_reset_n; wire tb_mkm_spi_sclk; @@ -119,6 +121,11 @@ module tb_keywrap_mkm(); begin : sys_monitor cycle_ctr = cycle_ctr + 1; + if (show_spi) + begin + $display("spi_clk: 0x%01x, spi_cs_n: 0x%01x, spi_do: 0x%01x, spi_di: 0x%01x", + tb_mkm_spi_sclk, tb_mkm_spi_cs_n, tb_mkm_spi_do, tb_mkm_spi_di); + end #(CLK_PERIOD); end @@ -135,6 +142,8 @@ module tb_keywrap_mkm(); error_ctr = 0; tc_ctr = 0; + show_spi = 0; + tb_clk = 1'h0; tb_reset_n = 1'h1; tb_mkm_spi_do = 1'h0; @@ -150,6 +159,45 @@ module tb_keywrap_mkm(); endtask // init_sim + //---------------------------------------------------------------- + // reset_dut() + // + // Toggle reset to put the DUT into a well known state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("TB: Resetting dut."); + tb_reset_n = 0; + #(2 * CLK_PERIOD); + tb_reset_n = 1; + end + endtask // reset_dut + + + //---------------------------------------------------------------- + // test_auto_load + //---------------------------------------------------------------- + task test_auto_load; + begin + tc_ctr = tc_ctr + 1; + + $display("TEST AUTO-LOAD START"); + $display("Check that correct ICV is generated for a single block message."); + + // Observe SPI for a number of cycles. Reset the DUT during monitoring. + show_spi = 1; + #(10 * CLK_PERIOD); + reset_dut(); + #(100 * CLK_PERIOD); + show_spi = 0; + + $display("TEST AUTO-LOAD END"); + $display(""); + end + endtask // auto_load + + + //---------------------------------------------------------------- // main //---------------------------------------------------------------- @@ -160,6 +208,7 @@ module tb_keywrap_mkm(); $display(""); init_sim(); + test_auto_load(); $display(""); $display("*** Keywrap mkmif wrapper testbench done. ***"); -- cgit v1.2.3 From 8b4f7c06886b3cb937d11fe9d2bd9a4f62a6d621 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 6 Nov 2018 14:30:53 +0100 Subject: Trigger read operation when we should read. --- src/rtl/keywrap_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index cf6e00a..378a61a 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -465,7 +465,7 @@ module keywrap_core #(parameter MEM_BITS = 11) if (read) begin - mkm_write = 1'h1; + mkm_read = 1'h1; ready_new = 1'h0; ready_we = 1'h1; mkm_read = 1'h1; -- cgit v1.2.3 From 42d63504f02f895a7b89dc164571c4b0d21cf8d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 6 Nov 2018 16:40:14 +0100 Subject: Fixed incorrect address used for the key. Added testcase to verify reading of status word. --- src/rtl/keywrap_mkmif.v | 4 ++-- src/tb/tb_keywrap_mkmif.v | 40 +++++++++++++++++++++++++++++++++++----- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index ad2121e..e2b9302 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -331,7 +331,7 @@ module keywrap_mkmif ( if (key_word_ctr_reg < 8) begin mkm_read_op = 1'h1; - mkm_addr_new = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0}; + mkm_addr_new = MKM_KEY_BASE_WORD + {key_word_ctr_reg, 2'h0}; mkm_addr_we = 1'h1; keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY_WAIT; keywrap_mkmif_ctrl_we = 1'h1; @@ -361,7 +361,7 @@ module keywrap_mkmif ( if (key_word_ctr_reg < 8) begin mkm_write_op = 1'h1; - mkm_addr_new = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0}; + mkm_addr_new = MKM_KEY_BASE_WORD + {key_word_ctr_reg, 2'h0}; mkm_addr_we = 1'h1; mkm_write_data_new = wr_key[key_word_ctr_reg * 32 +: 32]; mkm_write_data_we = 1'h1; diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 8bd3a05..e917c2c 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -182,9 +182,9 @@ module tb_keywrap_mkm(); tc_ctr = tc_ctr + 1; $display("TEST AUTO-LOAD START"); - $display("Check that correct ICV is generated for a single block message."); + $display("Check that key and key status is read automatically after reset."); - // Observe SPI for a number of cycles. Reset the DUT during monitoring. + // Observe SPI for a number of cycles. Reset the DUT during observation. show_spi = 1; #(10 * CLK_PERIOD); reset_dut(); @@ -197,21 +197,51 @@ module tb_keywrap_mkm(); endtask // auto_load + //---------------------------------------------------------------- + // test_write_status + //---------------------------------------------------------------- + task test_write_status; + begin + tc_ctr = tc_ctr + 1; + + $display("TEST WRITE STATUS START"); + $display("Check that we can write the key status word."); + + // Observe SPI for a number of cycles. Reset the DUT during observation. + show_spi = 1; + #(10 * CLK_PERIOD); + + tb_key_status = 1'h0; + tb_write = 1'h1; + tb_wr_status = 32'hdeadbeef; + + #(CLK_PERIOD); + tb_write = 1'h0; + + #(100 * CLK_PERIOD); + show_spi = 0; + + $display("TEST WRITE STATUS END"); + $display(""); + end + endtask // test_write_status + //---------------------------------------------------------------- // main //---------------------------------------------------------------- initial begin : main - $display(" -= Testbench for Keywrap mkmif wrapper started =-"); - $display(" ================================================"); + $display(" -= Testbench for Keywrap mkmif integration started =-"); + $display(" ===================================================="); $display(""); init_sim(); test_auto_load(); + test_write_status(); $display(""); - $display("*** Keywrap mkmif wrapper testbench done. ***"); + $display("*** Keywrap mkmif integration testbench done. ***"); $finish; end // main -- cgit v1.2.3 From 038eb4f4f4e5ca2cf6ad80e02091df0a34e6bde3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 13 Nov 2018 13:42:16 +0100 Subject: Adding README that describes the purpose of the dir and how to get the vendor specific memory model we need here. --- src/tech/README.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 src/tech/README.md diff --git a/src/tech/README.md b/src/tech/README.md new file mode 100644 index 0000000..0e04542 --- /dev/null +++ b/src/tech/README.md @@ -0,0 +1,14 @@ +README.md +========= +This dir is where the vendor specific Verilog memory model should be +stored. + +The memory used is the [Microchip +23K640](https://www.microchip.com/wwwproducts/en/23A640) a 64kbit, +SPI-connected serial SRAM. + +The Verilog memory model can be downloaded from that webpage or [by +clicking on this link](http://ww1.microchip.com/downloads/en/DeviceDoc/23x640_Verilog_Model.zip). + +Download and unzip the file in this directory. This should produce two +files, 23A640.v and 23K640.v. The one needed for simulation is 23K640.v -- cgit v1.2.3 From 33a7ad0aa4f30582d0858ca31a442316fe075396 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 22 Nov 2018 15:37:26 +0100 Subject: Adding outputs to observe dut API. Adding support in Makefile for using the vendor supplied memory model. --- src/tb/tb_keywrap_mkmif.v | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index e917c2c..faef1df 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -37,7 +37,10 @@ // //====================================================================== -module tb_keywrap_mkm(); +// We need this since the specific memory module sets timescale. +`timescale 1ns/10ps + +module tb_keywrap_mkmif(); //---------------------------------------------------------------- // Parameters. @@ -56,12 +59,13 @@ module tb_keywrap_mkm(); integer tc_ctr; integer show_spi; + integer show_dut_state; reg tb_clk; reg tb_reset_n; wire tb_mkm_spi_sclk; wire tb_mkm_spi_cs_n; - reg tb_mkm_spi_do; + wire tb_mkm_spi_do; wire tb_mkm_spi_di; reg tb_init; reg tb_read; @@ -73,6 +77,8 @@ module tb_keywrap_mkm(); reg [255 : 0] tb_wr_key; wire [255 : 0] tb_rd_key; + wire mem_hold_n = 1'b1; + //---------------------------------------------------------------- // Device Under Test. @@ -99,6 +105,18 @@ module tb_keywrap_mkm(); ); + //---------------------------------------------------------------- + // Memory model. See README.md in src/tech for info on how + // to get the vendor specific model needed here. + //---------------------------------------------------------------- + M23K640 memory(.SI(tb_mkm_spi_di), + .SO(tb_mkm_spi_do), + .SCK(tb_mkm_spi_sclk), + .CS_N(tb_mkm_spi_cs_n), + .HOLD_N(mem_hold_n), + .RESET(tb_reset_n)); + + //---------------------------------------------------------------- // clk_gen // @@ -120,11 +138,21 @@ module tb_keywrap_mkm(); always begin : sys_monitor cycle_ctr = cycle_ctr + 1; + $display("cycle: %08d", cycle_ctr); + + if (show_dut_state) + begin + $display("init: 0x%01x read: 0x%01x write: 0x%01x key_status: 0x%01x", + dut.init, dut.read, dut.write, dut.key_status); + $display("ready: 0x%01x ctrl_state: 0x%02x", dut.ready, dut.keywrap_mkmif_ctrl_reg); + end if (show_spi) begin $display("spi_clk: 0x%01x, spi_cs_n: 0x%01x, spi_do: 0x%01x, spi_di: 0x%01x", tb_mkm_spi_sclk, tb_mkm_spi_cs_n, tb_mkm_spi_do, tb_mkm_spi_di); + $display(); + $display(); end #(CLK_PERIOD); end @@ -142,11 +170,11 @@ module tb_keywrap_mkm(); error_ctr = 0; tc_ctr = 0; - show_spi = 0; + show_spi = 0; + show_dut_state = 1; tb_clk = 1'h0; tb_reset_n = 1'h1; - tb_mkm_spi_do = 1'h0; tb_init = 1'h0; tb_read = 1'h0; tb_write = 1'h0; @@ -166,10 +194,11 @@ module tb_keywrap_mkm(); //---------------------------------------------------------------- task reset_dut; begin - $display("TB: Resetting dut."); + $display("Asserting reset."); tb_reset_n = 0; #(2 * CLK_PERIOD); tb_reset_n = 1; + $display("Deasserting reset."); end endtask // reset_dut @@ -183,6 +212,7 @@ module tb_keywrap_mkm(); $display("TEST AUTO-LOAD START"); $display("Check that key and key status is read automatically after reset."); + $display(); // Observe SPI for a number of cycles. Reset the DUT during observation. show_spi = 1; @@ -245,8 +275,8 @@ module tb_keywrap_mkm(); $finish; end // main -endmodule // tb_keywrap_mkm +endmodule // tb_keywrap_mkmif //====================================================================== -// EOF tb_keywrap_mkm.v +// EOF tb_keywrap_mkmif.v //====================================================================== -- cgit v1.2.3 From 8a8caf46d761a583f7ec320f8744bd7082090dd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 07:36:22 +0100 Subject: Adding vendor mem model. --- toolruns/Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/toolruns/Makefile b/toolruns/Makefile index a6dcf00..170e4bf 100755 --- a/toolruns/Makefile +++ b/toolruns/Makefile @@ -37,6 +37,9 @@ # #=================================================================== +VENDOR_MEM_PATH = ../src/tech +VENDOR_MEM_SRC = $(VENDOR_MEM_PATH)/23K640.v + MKMIF_PATH = ../../mkmif/src/rtl MKMIF_SRC = $(MKMIF_PATH)/mkmif_core.v $(MKMIF_PATH)/mkmif_spi.v @@ -76,8 +79,8 @@ mem.sim: $(TB_MEM_SRC) $(MEM_SRC) $(CC) $(CC_FLAGS) -o mem.sim $(TB_MEM_SRC) $(MEM_SRC) -mkmif.sim: $(TB_KEYWRAP_MKMIF_SRC) $(KEYWRAP_MKMIF_SRC) $(MKMIF_SRC) - $(CC) $(CC_FLAGS) -o mkmif.sim $(TB_KEYWRAP_MKMIF_SRC) $(KEYWRAP_MKMIF_SRC) $(MKMIF_SRC) +mkmif.sim: $(TB_KEYWRAP_MKMIF_SRC) $(KEYWRAP_MKMIF_SRC) $(MKMIF_SRC) $(VENDOR_MEM_SRC) + $(CC) $(CC_FLAGS) -o mkmif.sim $(TB_KEYWRAP_MKMIF_SRC) $(KEYWRAP_MKMIF_SRC) $(MKMIF_SRC) $(VENDOR_MEM_SRC) sim-top: top.sim -- cgit v1.2.3 From 42e3fcaaec5fe0ae0788d3e1c02da1751cbc9c5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 07:38:00 +0100 Subject: Adding test case for mem init. Removing auto-load test case since the dut does not support auto load. Updating the write status test case to use wait_ready() for dut status. --- src/tb/tb_keywrap_mkmif.v | 48 ++++++++++++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index faef1df..1acce3d 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -204,27 +204,40 @@ module tb_keywrap_mkmif(); //---------------------------------------------------------------- - // test_auto_load + // wait_ready() + // + // Wait for ready to be asserted. + //---------------------------------------------------------------- + task wait_ready; + begin + while (!tb_ready) + #(CLK_PERIOD); + + $display("Ready has been set."); + end + endtask // wait_ready + + + //---------------------------------------------------------------- + // test_init_mem //---------------------------------------------------------------- - task test_auto_load; + task test_init_mem; begin tc_ctr = tc_ctr + 1; - $display("TEST AUTO-LOAD START"); - $display("Check that key and key status is read automatically after reset."); + $display("TEST INIT-MEM START"); + $display("Check that the memory is configured when pulling init."); $display(); - // Observe SPI for a number of cycles. Reset the DUT during observation. - show_spi = 1; - #(10 * CLK_PERIOD); - reset_dut(); - #(100 * CLK_PERIOD); - show_spi = 0; + tb_init = 1'h1; + #(CLK_PERIOD); + tb_init = 1'h0; + wait_ready(); - $display("TEST AUTO-LOAD END"); + $display("TEST INIT-MEM END"); $display(""); end - endtask // auto_load + endtask // test_init_mem //---------------------------------------------------------------- @@ -234,24 +247,25 @@ module tb_keywrap_mkmif(); begin tc_ctr = tc_ctr + 1; - $display("TEST WRITE STATUS START"); + $display("TEST WRITE-STATUS START"); $display("Check that we can write the key status word."); // Observe SPI for a number of cycles. Reset the DUT during observation. show_spi = 1; #(10 * CLK_PERIOD); + $display("Trying to write 0xdeadbeef to status address."); + tb_wr_status = 32'hdeadbeef; tb_key_status = 1'h0; tb_write = 1'h1; - tb_wr_status = 32'hdeadbeef; #(CLK_PERIOD); tb_write = 1'h0; - #(100 * CLK_PERIOD); + wait_ready(); show_spi = 0; - $display("TEST WRITE STATUS END"); + $display("TEST WRITE-STATUS END"); $display(""); end endtask // test_write_status @@ -267,7 +281,7 @@ module tb_keywrap_mkmif(); $display(""); init_sim(); - test_auto_load(); + test_init_mem(); test_write_status(); $display(""); -- cgit v1.2.3 From 4e4a87a035e98cc8fbcc6d33b9c6009919213a64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 08:17:37 +0100 Subject: Enabled spi observation and can see that SPI interface is alive when pulling init. --- src/tb/tb_keywrap_mkmif.v | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 1acce3d..ccb8ff3 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -195,10 +195,14 @@ module tb_keywrap_mkmif(); task reset_dut; begin $display("Asserting reset."); + $display(); + tb_reset_n = 0; #(2 * CLK_PERIOD); tb_reset_n = 1; + $display("Deasserting reset."); + $display(); end endtask // reset_dut @@ -210,10 +214,13 @@ module tb_keywrap_mkmif(); //---------------------------------------------------------------- task wait_ready; begin + #(2 * CLK_PERIOD); + while (!tb_ready) #(CLK_PERIOD); $display("Ready has been set."); + $display(); end endtask // wait_ready @@ -229,10 +236,12 @@ module tb_keywrap_mkmif(); $display("Check that the memory is configured when pulling init."); $display(); + show_spi = 1; tb_init = 1'h1; #(CLK_PERIOD); tb_init = 1'h0; wait_ready(); + show_spi = 0; $display("TEST INIT-MEM END"); $display(""); @@ -281,6 +290,7 @@ module tb_keywrap_mkmif(); $display(""); init_sim(); + reset_dut(); test_init_mem(); test_write_status(); -- cgit v1.2.3 From e3ce9cd91fe4da7917dd72920f0a9d0540831c37 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 10:06:30 +0100 Subject: Added observation of mem internal control states. --- src/tb/tb_keywrap_mkmif.v | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index ccb8ff3..06e3356 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -60,6 +60,7 @@ module tb_keywrap_mkmif(); integer show_spi; integer show_dut_state; + integer show_mem_state; reg tb_clk; reg tb_reset_n; @@ -109,12 +110,12 @@ module tb_keywrap_mkmif(); // Memory model. See README.md in src/tech for info on how // to get the vendor specific model needed here. //---------------------------------------------------------------- - M23K640 memory(.SI(tb_mkm_spi_di), - .SO(tb_mkm_spi_do), - .SCK(tb_mkm_spi_sclk), - .CS_N(tb_mkm_spi_cs_n), - .HOLD_N(mem_hold_n), - .RESET(tb_reset_n)); + M23K640 mem(.SI(tb_mkm_spi_di), + .SO(tb_mkm_spi_do), + .SCK(tb_mkm_spi_sclk), + .CS_N(tb_mkm_spi_cs_n), + .HOLD_N(mem_hold_n), + .RESET(tb_reset_n)); //---------------------------------------------------------------- @@ -147,13 +148,21 @@ module tb_keywrap_mkmif(); $display("ready: 0x%01x ctrl_state: 0x%02x", dut.ready, dut.keywrap_mkmif_ctrl_reg); end + if (show_mem_state) + begin + $display("BitCounter: %08d InstRegister: 0x%01x AddrRegister: 0x%02x", + mem.BitCounter, mem.InstRegister, mem.AddrRegister); + $display("DataShifterI: 0x%02x DataShifterO: 0x%01x", + mem.DataShifterI, mem.DataShifterO); + end + if (show_spi) begin $display("spi_clk: 0x%01x, spi_cs_n: 0x%01x, spi_do: 0x%01x, spi_di: 0x%01x", tb_mkm_spi_sclk, tb_mkm_spi_cs_n, tb_mkm_spi_do, tb_mkm_spi_di); - $display(); - $display(); end + + $display("\n"); #(CLK_PERIOD); end @@ -172,6 +181,7 @@ module tb_keywrap_mkmif(); show_spi = 0; show_dut_state = 1; + show_mem_state = 1; tb_clk = 1'h0; tb_reset_n = 1'h1; -- cgit v1.2.3 From 88d1cb6b6cc58050b406bb0d5134d727d4eca684 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 10:34:14 +0100 Subject: Adding task to dump parts of the contents of the serial memory. --- src/tb/tb_keywrap_mkmif.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 06e3356..55305ff 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -167,6 +167,26 @@ module tb_keywrap_mkmif(); end + //---------------------------------------------------------------- + // dump_mem + // + // Dump the contents of the memory model. + //---------------------------------------------------------------- + task dump_mem; + begin : dump_mem + integer i; + + $display("Contents of the first 256 bytes in the serial memory:"); + for (i = 0 ; i < 256 ; i = i + 8) + $display("0x%01x 0x%01x 0x%01x 0x%01x 0x%01x 0x%01x 0x%01x 0x%01x", + mem.MemoryBlock[i], mem.MemoryBlock[i + 1], + mem.MemoryBlock[i + 2], mem.MemoryBlock[i + 3], + mem.MemoryBlock[i + 4], mem.MemoryBlock[i + 5], + mem.MemoryBlock[i + 6], mem.MemoryBlock[i + 7]); + end + endtask // dump_mem + + //---------------------------------------------------------------- // init_sim() // @@ -301,8 +321,10 @@ module tb_keywrap_mkmif(); init_sim(); reset_dut(); + dump_mem(); test_init_mem(); test_write_status(); + dump_mem(); $display(""); $display("*** Keywrap mkmif integration testbench done. ***"); -- cgit v1.2.3 From f67001b76c6b6a7764bbea7fdec5d5d0e3ce9792 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 11:08:24 +0100 Subject: Updated display of states. We can now observe correct init of the memory. --- src/tb/tb_keywrap_mkmif.v | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 55305ff..b22be82 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -143,21 +143,27 @@ module tb_keywrap_mkmif(); if (show_dut_state) begin + $display("DUT control state:"); $display("init: 0x%01x read: 0x%01x write: 0x%01x key_status: 0x%01x", dut.init, dut.read, dut.write, dut.key_status); $display("ready: 0x%01x ctrl_state: 0x%02x", dut.ready, dut.keywrap_mkmif_ctrl_reg); + $display(); end - if (show_mem_state) begin - $display("BitCounter: %08d InstRegister: 0x%01x AddrRegister: 0x%02x", - mem.BitCounter, mem.InstRegister, mem.AddrRegister); - $display("DataShifterI: 0x%02x DataShifterO: 0x%01x", - mem.DataShifterI, mem.DataShifterO); + $display("Memory control state:"); + $display("Hold: 0x%1x BitCounter: 0x%04x", mem.Hold, mem.BitCounter); + $display("DataShifterI: 0x%02x DataShifterO: 0x%1x", mem.DataShifterI, mem.DataShifterO); + $display("InstRegister: 0x%1x AddrRegister: 0x%02x", mem.InstRegister, mem.AddrRegister); + $display("OpMode0: 0x%1x OpMode1: 0x%1x", mem.OpMode0, mem.OpMode1); + $display("InstructionREAD: 0x%1x InstructionRDSR: 0x%1x", mem.InstructionREAD, mem.InstructionRDSR); + $display("InstructionWRSR: 0x%1x InstructionWRITE: 0x%1x", mem.InstructionWRSR, mem.InstructionWRITE); + $display(); end if (show_spi) begin + $display("SPI interface state:"); $display("spi_clk: 0x%01x, spi_cs_n: 0x%01x, spi_do: 0x%01x, spi_di: 0x%01x", tb_mkm_spi_sclk, tb_mkm_spi_cs_n, tb_mkm_spi_do, tb_mkm_spi_di); end -- cgit v1.2.3 From e8fb3bbedca650c3b5fdf0e620bdc231bc85fd55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 23 Nov 2018 12:55:36 +0100 Subject: Added ability observe mkmif state. Realized that the write operation handler was under read operation handling. Fixed this and now status write works. We can observe 0xdeadbeef in the memory after status write operation. --- src/rtl/keywrap_mkmif.v | 40 +++++++++++++++++++++++----------------- src/tb/tb_keywrap_mkmif.v | 10 ++++++++++ 2 files changed, 33 insertions(+), 17 deletions(-) diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index e2b9302..88af6f8 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -282,27 +282,33 @@ module keywrap_mkmif ( keywrap_mkmif_ctrl_new = CTRL_READ_STATUS_WAIT; keywrap_mkmif_ctrl_we = 1'h1; end + end + + if (write) + begin + ready_new = 1'h0; + ready_we = 1'h1; - if (write) - if (key_status) - begin - key_word_ctr_rst = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; - keywrap_mkmif_ctrl_we = 1'h1; - end - else - begin - mkm_write_op = 1'h1; - mkm_addr_new = MKM_STATUS_WORD; - mkm_addr_we = 1'h1; - mkm_write_data_new = wr_status; - mkm_write_data_we = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WAIT; - keywrap_mkmif_ctrl_we = 1'h1; - end + if (key_status) + begin + key_word_ctr_rst = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + mkm_write_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD; + mkm_addr_we = 1'h1; + mkm_write_data_new = wr_status; + mkm_write_data_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end end end + CTRL_WAIT: begin if (mkm_ready) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index b22be82..89e93c7 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -61,6 +61,7 @@ module tb_keywrap_mkmif(); integer show_spi; integer show_dut_state; integer show_mem_state; + integer show_mkm_state; reg tb_clk; reg tb_reset_n; @@ -149,6 +150,14 @@ module tb_keywrap_mkmif(); $display("ready: 0x%01x ctrl_state: 0x%02x", dut.ready, dut.keywrap_mkmif_ctrl_reg); $display(); end + + if (show_mkm_state) + begin + $display("MKM control state:"); + $display("ready: 0x%1x ctrl: 0x%1x", dut.mkm_ready, dut.mkm.mkmif_ctrl_reg); + $display(); + end + if (show_mem_state) begin $display("Memory control state:"); @@ -208,6 +217,7 @@ module tb_keywrap_mkmif(); show_spi = 0; show_dut_state = 1; show_mem_state = 1; + show_mkm_state = 1; tb_clk = 1'h0; tb_reset_n = 1'h1; -- cgit v1.2.3 From 0fb1cd7cddf85af93a29959b66b0295ae0021e45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 27 Nov 2018 13:47:35 +0100 Subject: Adding check that correct status word was written into the serial memory. --- src/tb/tb_keywrap_mkmif.v | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 89e93c7..79083e4 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -216,8 +216,8 @@ module tb_keywrap_mkmif(); show_spi = 0; show_dut_state = 1; - show_mem_state = 1; - show_mkm_state = 1; + show_mem_state = 0; + show_mkm_state = 0; tb_clk = 1'h0; tb_reset_n = 1'h1; @@ -282,7 +282,7 @@ module tb_keywrap_mkmif(); $display("Check that the memory is configured when pulling init."); $display(); - show_spi = 1; + show_spi = 0; tb_init = 1'h1; #(CLK_PERIOD); tb_init = 1'h0; @@ -306,7 +306,7 @@ module tb_keywrap_mkmif(); $display("Check that we can write the key status word."); // Observe SPI for a number of cycles. Reset the DUT during observation. - show_spi = 1; + show_spi = 0; #(10 * CLK_PERIOD); $display("Trying to write 0xdeadbeef to status address."); @@ -320,6 +320,16 @@ module tb_keywrap_mkmif(); wait_ready(); show_spi = 0; + // Check content in memory. + if ((mem.MemoryBlock[0] == 8'hde) && (mem.MemoryBlock[1] == 8'had) && + (mem.MemoryBlock[2] == 8'hbe) && (mem.MemoryBlock[3] == 8'hef)) + $display("Correct status word was written into the memory."); + else + begin + $display("Correct status word was NOT written into the memory."); + error_ctr = error_ctr + 1; + end + $display("TEST WRITE-STATUS END"); $display(""); end -- cgit v1.2.3 From 88c15a5ff837dc6871f7ca8caf4610a4e2d056fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 27 Nov 2018 13:48:22 +0100 Subject: Adding test that tries to write a key into the serial memory. --- src/tb/tb_keywrap_mkmif.v | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 79083e4..3289a77 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -336,6 +336,39 @@ module tb_keywrap_mkmif(); endtask // test_write_status + //---------------------------------------------------------------- + // test_write_key + //---------------------------------------------------------------- + task test_write_key; + begin + tc_ctr = tc_ctr + 1; + + $display("TEST WRITE-KEY START"); + $display("Check that we can write the key words."); + + // Observe SPI for a number of cycles. Reset the DUT during observation. + show_spi = 0; + #(10 * CLK_PERIOD); + + $display("Trying to write test key to key address."); + $display("test key: 0x01020304 0xaa55aa55 0x00ff00ff 0x0f0e0d0c"); + $display(" 0x11121314 0x55aa55aa 0x11ee11ee 0x1f1e1d1c"); + + tb_wr_key = 256'h01020304_aa55aa55_00ff00ff_0f0e0d0c_11121314_55aa55aa_11ee11ee_1f1e1d1c; + tb_key_status = 1'h1; + tb_write = 1'h1; + + #(CLK_PERIOD); + tb_write = 1'h0; + + wait_ready(); + show_spi = 0; + + $display("TEST WRITE-KEY END"); + $display(""); + end + endtask // test_write_key + //---------------------------------------------------------------- // main //---------------------------------------------------------------- @@ -350,6 +383,7 @@ module tb_keywrap_mkmif(); dump_mem(); test_init_mem(); test_write_status(); + test_write_key(); dump_mem(); $display(""); -- cgit v1.2.3 From 0d2aa16a71c1f0ca183a71c3d5460c6ff1a2f245 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Fri, 7 Dec 2018 10:03:23 +0100 Subject: Solved event loop. --- src/rtl/keywrap_mkmif.v | 142 ++++++++++++++++++++++++++++++---------------- src/tb/tb_keywrap_mkmif.v | 42 +++++++++++++- 2 files changed, 131 insertions(+), 53 deletions(-) diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v index 88af6f8..2f7bebf 100644 --- a/src/rtl/keywrap_mkmif.v +++ b/src/rtl/keywrap_mkmif.v @@ -63,13 +63,16 @@ module keywrap_mkmif ( //---------------------------------------------------------------- // Paramenters and local defines. //---------------------------------------------------------------- - localparam CTRL_IDLE = 3'h0; - localparam CTRL_WAIT = 3'h1; - localparam CTRL_READ_STATUS_WAIT = 3'h2; - localparam CTRL_READ_KEY = 3'h3; - localparam CTRL_READ_KEY_WAIT = 3'h4; - localparam CTRL_WRITE_KEY = 3'h5; - localparam CTRL_WRITE_KEY_WAIT = 3'h6; + localparam CTRL_IDLE = 4'h0; + localparam CTRL_WAIT = 4'h1; + localparam CTRL_INIT = 4'h2; + localparam CTRL_READ = 4'h3; + localparam CTRL_READ_STATUS_WAIT = 4'h4; + localparam CTRL_READ_KEY = 4'h5; + localparam CTRL_READ_KEY_WAIT = 4'h6; + localparam CTRL_WRITE = 4'h8; + localparam CTRL_WRITE_KEY = 4'h9; + localparam CTRL_WRITE_KEY_WAIT = 4'ha; // Addresses for storage in the mkm localparam MKM_STATUS_WORD = 16'h00; @@ -106,10 +109,14 @@ module keywrap_mkmif ( reg ready_new; reg ready_we; - reg [2 : 0] keywrap_mkmif_ctrl_reg; - reg [2 : 0] keywrap_mkmif_ctrl_new; + reg [3 : 0] keywrap_mkmif_ctrl_reg; + reg [3 : 0] keywrap_mkmif_ctrl_new; reg keywrap_mkmif_ctrl_we; + reg init_op_reg; + reg read_op_reg; + reg write_op_reg; + //---------------------------------------------------------------- // Wires. @@ -136,9 +143,9 @@ module keywrap_mkmif ( .spi_do(mkm_spi_do), .spi_di(mkm_spi_di), - .init_op(mkm_init_op), - .read_op(mkm_read_op), - .write_op(mkm_write_op), + .init_op(init_op_reg), + .read_op(read_op_reh), + .write_op(write_op_reg), .ready(mkm_ready), .valid(mkm_valid), @@ -178,11 +185,18 @@ module keywrap_mkmif ( mkm_addr_reg <= 16'h0; mkm_write_data_reg <= 32'h0; key_word_ctr_reg <= 3'h0; + init_op_reg <= 1'h0; + read_op_reg <= 1'h0; + write_op_reg <= 1'h0; keywrap_mkmif_ctrl_reg <= CTRL_IDLE; end else begin + init_op_reg <= mkm_init_op; + read_op_reg <= mkm_read_op; + write_op_reg <= mkm_write_op; + if (ready_we) ready_reg <= ready_new; @@ -259,52 +273,50 @@ module keywrap_mkmif ( mkm_init_op = 1'h1; ready_new = 1'h0; ready_we = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_new = CTRL_INIT; keywrap_mkmif_ctrl_we = 1'h1; end if (read) begin - ready_new = 1'h0; - ready_we = 1'h1; - - if (key_status) - begin - key_word_ctr_rst = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_READ_KEY; - keywrap_mkmif_ctrl_we = 1'h1; - end - else - begin - mkm_read_op = 1'h1; - mkm_addr_new = MKM_STATUS_WORD; - mkm_addr_we = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_READ_STATUS_WAIT; - keywrap_mkmif_ctrl_we = 1'h1; - end + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_READ; + keywrap_mkmif_ctrl_we = 1'h1; end if (write) begin - ready_new = 1'h0; - ready_we = 1'h1; - - if (key_status) - begin - key_word_ctr_rst = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; - keywrap_mkmif_ctrl_we = 1'h1; - end - else - begin - mkm_write_op = 1'h1; - mkm_addr_new = MKM_STATUS_WORD; - mkm_addr_we = 1'h1; - mkm_write_data_new = wr_status; - mkm_write_data_we = 1'h1; - keywrap_mkmif_ctrl_new = CTRL_WAIT; - keywrap_mkmif_ctrl_we = 1'h1; - end + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + + CTRL_INIT: + begin + keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + + + CTRL_READ: + begin + if (key_status) + begin + key_word_ctr_rst = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_READ_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + mkm_read_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD; + mkm_addr_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_READ_STATUS_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; end end @@ -320,8 +332,13 @@ module keywrap_mkmif ( end end + CTRL_READ_STATUS_WAIT: begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_IDLE; + keywrap_mkmif_ctrl_we = 1'h1; if (mkm_ready) begin status_we = 1'h1; @@ -332,6 +349,7 @@ module keywrap_mkmif ( end end + CTRL_READ_KEY: begin if (key_word_ctr_reg < 8) @@ -351,6 +369,7 @@ module keywrap_mkmif ( end end + CTRL_READ_KEY_WAIT: begin if (mkm_ready) @@ -362,6 +381,28 @@ module keywrap_mkmif ( end end + + CTRL_WRITE: + begin + if (key_status) + begin + key_word_ctr_rst = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY; + keywrap_mkmif_ctrl_we = 1'h1; + end + else + begin + mkm_write_op = 1'h1; + mkm_addr_new = MKM_STATUS_WORD; + mkm_addr_we = 1'h1; + mkm_write_data_new = wr_status; + mkm_write_data_we = 1'h1; + keywrap_mkmif_ctrl_new = CTRL_WAIT; + keywrap_mkmif_ctrl_we = 1'h1; + end + end + + CTRL_WRITE_KEY: begin if (key_word_ctr_reg < 8) @@ -383,6 +424,7 @@ module keywrap_mkmif ( end end + CTRL_WRITE_KEY_WAIT: begin if (mkm_ready) @@ -393,9 +435,9 @@ module keywrap_mkmif ( end end + default: begin - end endcase // case (keywrap_mkmif_ctrl_reg) end // keywrap_mkmif_ctrl diff --git a/src/tb/tb_keywrap_mkmif.v b/src/tb/tb_keywrap_mkmif.v index 3289a77..b275499 100644 --- a/src/tb/tb_keywrap_mkmif.v +++ b/src/tb/tb_keywrap_mkmif.v @@ -215,7 +215,7 @@ module tb_keywrap_mkmif(); tc_ctr = 0; show_spi = 0; - show_dut_state = 1; + show_dut_state = 0; show_mem_state = 0; show_mkm_state = 0; @@ -303,7 +303,7 @@ module tb_keywrap_mkmif(); tc_ctr = tc_ctr + 1; $display("TEST WRITE-STATUS START"); - $display("Check that we can write the key status word."); + $display("Check that we can write the status word."); // Observe SPI for a number of cycles. Reset the DUT during observation. show_spi = 0; @@ -336,6 +336,41 @@ module tb_keywrap_mkmif(); endtask // test_write_status + //---------------------------------------------------------------- + // test_read_status + // Note: This test should be called after test_write_status. + // If not the contents of the memort will be undefined. + //---------------------------------------------------------------- + task test_read_status; + begin + tc_ctr = tc_ctr + 1; + + $display("TEST READ-STATUS START"); + $display("Check that we can read the status word."); + + // Observe SPI for a number of cycles. Reset the DUT during observation. + show_spi = 0; + show_dut_state = 1; + #(10 * CLK_PERIOD); + + $display("Trying to read 0xdeadbeef from the status address."); + tb_key_status = 1'h0; + tb_read = 1'h1; + + #(CLK_PERIOD); + tb_read = 1'h0; + + wait_ready(); + show_spi = 0; + + $display("The word read: 0x%04x", tb_rd_status); + + $display("TEST READ-STATUS END"); + $display(""); + end + endtask // test_read_status + + //---------------------------------------------------------------- // test_write_key //---------------------------------------------------------------- @@ -383,7 +418,8 @@ module tb_keywrap_mkmif(); dump_mem(); test_init_mem(); test_write_status(); - test_write_key(); +// test_read_status(); +// test_write_key(); dump_mem(); $display(""); -- cgit v1.2.3