diff options
Diffstat (limited to 'src/tb/tb_keywrap.v')
| -rw-r--r-- | src/tb/tb_keywrap.v | 70 |
1 files changed, 52 insertions, 18 deletions
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v index 867b4a3..e0b82c4 100644 --- a/src/tb/tb_keywrap.v +++ b/src/tb/tb_keywrap.v @@ -39,9 +39,10 @@ module tb_keywrap(); - parameter DEBUG = 0; - parameter DUMP_TOP = 0; - parameter DUMP_CORE = 0; + parameter DEBUG = 1; + parameter DUMP_TOP = 0; + parameter DUMP_CORE = 0; + parameter DUMP_TIMEOUT = 1; parameter CLK_HALF_PERIOD = 1; parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; @@ -300,6 +301,22 @@ module tb_keywrap(); $display("keywrap_core_ctrl_we = 0x%0x", dut.core.keywrap_core_ctrl_we); end + if (DUMP_TIMEOUT) + begin + $display("timeout signals:"); + + $display("api_timeout_reg = 0x%04x api_timeout_we = 0x%x", dut.timeout_reg, dut.timeout_we); + $display("timeout = 0x%04x ping = 0x%x zeroise = 0x%x loaded = 0x%x", + dut.core.timeout, dut.core.ping, dut.core.zeroise, dut.core.loaded); + $display("key_timeout_ctr_reg = 0x%04x key_timeout_ctr_new = 0x%04x", + dut.core.key_timeout_ctr_reg, dut.core.key_timeout_ctr_new); + $display("key_timeout = 0x%x key_timeout_ctr_we = 0x%x key_timeout_ctr_set = 0x%x key_timeout_ctr_dec = 0x%x", + dut.core.key_timeout, dut.core.key_timeout_ctr_we, dut.core.key_timeout_ctr_set, dut.core.key_timeout_ctr_dec); + + $display("keywrap_core_ctrl_reg = 0x%0x", dut.core.keywrap_core_ctrl_reg); + $display("keywrap_core_ctrl_new = 0x%0x", dut.core.keywrap_core_ctrl_new); + $display("keywrap_core_ctrl_we = 0x%0x", dut.core.keywrap_core_ctrl_we); + end $display(""); $display(""); end @@ -1178,10 +1195,14 @@ module tb_keywrap(); read_word(ADDR_STATUS); $display("Status register: 0x%032b", read_data); - // Set the key timeout to 6 * 16 = 96 cycles. - write_word(ADDR_TIMEOUT, 32'h00000006); + // Set the key timeout to 256 cycles. + write_word(ADDR_TIMEOUT, 32'hdeadbeef); + read_word(ADDR_TIMEOUT); + if (read_data != 32'hdeadbeef) + $display("Error. Timout value = 0x%04x, expected 0xdeadbeef", read_data); - $display("Contents of the key_mem[2]: 0x%016x", + // Display contents in key expansion register 2. + $display("Contents of the key_mem[2] before init: 0x%016x", dut.core.aes.keymem.key_mem[2]); // Initialize the AES engine (to expand the key). @@ -1193,27 +1214,27 @@ module tb_keywrap(); wait_ready(); $display("* Init done."); - // Display contents in one of the key expansion registers - $display("Contents of the key_mem[2]: 0x%016x", + // Display contents in key expansion register 2 again. + $display("Contents of the key_mem[2] after init: 0x%016x", dut.core.aes.keymem.key_mem[2]); // Check if key is loaded, according to the loaded flag. read_word(ADDR_STATUS); - $display("Status register: 0x%032b", read_data); + $display("Status register: 0b%032b", read_data); - // Display the counter a few times. - $display("Contents of the key_mem[2]: 0x%05x", + // Display the timeout counter a few times. + $display("Contents of timeout counter: 0x%04x", dut.core.key_timeout_ctr_reg); - #(10 * CLK_PERIOD); - $display("Contents of the key_mem[2]: 0x%05x", + #(2 * CLK_PERIOD); + $display("Contents of timeout counter: 0x%04x", dut.core.key_timeout_ctr_reg); - #(10 * CLK_PERIOD); - $display("Contents of the key_mem[2]: 0x%05x", + #(2 * CLK_PERIOD); + $display("Contents of timeout counter: 0x%04x", dut.core.key_timeout_ctr_reg); - #(10 * CLK_PERIOD); - $display("Contents of the key_mem[2]: 0x%05x", + #(2 * CLK_PERIOD); + $display("Contents of timeout counter: 0x%04x", dut.core.key_timeout_ctr_reg); - #(10 * CLK_PERIOD); + #(2 * CLK_PERIOD); read_word(ADDR_STATUS); $display("Status register: 0x%032b", read_data); @@ -1221,9 +1242,22 @@ module tb_keywrap(); // Display contents in one of the key expansion registers $display("Contents of the key_mem[2]: 0x%016x", dut.core.aes.keymem.key_mem[2]); + // Display contents in one of the key expansion registers + $display("Contents of the key_mem[2]: 0x%016x", + dut.core.aes.keymem.key_mem[2]); + // Display contents in one of the key expansion registers + $display("Contents of the key_mem[2]: 0x%016x", + dut.core.aes.keymem.key_mem[2]); #(40 * CLK_PERIOD); + // Set the key timeout to 16 cycles. + // Read status to perform ping. + write_word(ADDR_TIMEOUT, 32'h00000010); + read_word(ADDR_STATUS); + #(400 * CLK_PERIOD); + + read_word(ADDR_STATUS); $display("Status register: 0x%032b", read_data); |