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-rw-r--r--src/rtl/keywrap.v1
-rw-r--r--src/rtl/keywrap_core.v17
2 files changed, 9 insertions, 9 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 36e95bf..47c40d6 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -302,6 +302,7 @@ module keywrap #(parameter ADDR_BITS = 13)
a1_we = 1'h0;
tmp_read_data = 32'h0;
tmp_error = 1'h0;
+ timeout_we = 1'h0;
ping_new = 1'h0;
zeroise_new = 1'h0;
api_rd_delay_new = 32'h0;
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 5d628e2..866e132 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -123,8 +123,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
reg iteration_ctr_set;
reg iteration_ctr_rst;
- reg [35 : 0] key_timeout_ctr_reg;
- reg [35 : 0] key_timeout_ctr_new;
+ reg [31 : 0] key_timeout_ctr_reg;
+ reg [31 : 0] key_timeout_ctr_new;
reg key_timeout_ctr_we;
reg key_timeout_ctr_set;
reg key_timeout_ctr_dec;
@@ -219,7 +219,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
valid_reg <= 1'h1;
block_ctr_reg <= {(MEM_BITS - 1){1'h0}};
iteration_ctr_reg <= 3'h0;
- key_timeout_ctr_reg <= 36'h0;
+ key_timeout_ctr_reg <= 32'h0;
key_loaded_reg <= 1'h0;
keywrap_core_ctrl_reg <= CTRL_IDLE;
end
@@ -387,20 +387,19 @@ module keywrap_core #(parameter MEM_BITS = 11)
//----------------------------------------------------------------
always @*
begin : key_timeout_ctr
- key_timeout_ctr_new = 36'h0;
+ key_timeout_ctr_new = 32'h0;
key_timeout_ctr_we = 1'h0;
key_timeout = 1'h0;
- if (key_timeout_ctr_reg == 36'h0)
+ if (key_timeout_ctr_reg == 32'h0)
key_timeout = 1'h1;
if (key_timeout_ctr_set || ping)
begin
- key_timeout_ctr_new = {timeout, 4'h0};
+ key_timeout_ctr_new = timeout;
key_timeout_ctr_we = 1'h1;
end
-
- if (key_timeout_ctr_dec)
+ else if (key_timeout_ctr_dec)
begin
key_timeout_ctr_new = key_timeout_ctr_reg - 1'h1;
key_timeout_ctr_we = 1'h1;
@@ -452,7 +451,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
valid_new = 1'h0;
valid_we = 1'h1;
keywrap_core_ctrl_new = CTRL_ZERO_WAIT;
- keywrap_core_ctrl_we = 1'h0;
+ keywrap_core_ctrl_we = 1'h1;
end
else
begin