diff options
Diffstat (limited to 'src/rtl/keywrap_core.v')
| -rw-r--r-- | src/rtl/keywrap_core.v | 139 |
1 files changed, 121 insertions, 18 deletions
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v index b3e17f6..3abe93c 100644 --- a/src/rtl/keywrap_core.v +++ b/src/rtl/keywrap_core.v @@ -44,17 +44,28 @@ module keywrap_core #(parameter MEM_BITS = 11) input wire clk, input wire reset_n, + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + input wire init, input wire next, + input wire read, + input wire write, + input wire mkey_mstatus, + input wire mkey_key, input wire encdec, output wire ready, output wire valid, input wire [(MEM_BITS - 2) : 0] rlen, - input wire [255 : 0] key, input wire keylen, + input wire [31 : 0] status, + output wire [255 : 0] mkey, + output wire [31 : 0] mstatus, input wire [63 : 0] a_init, output wire [63 : 0] a_result, @@ -71,17 +82,19 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- localparam MAX_ITERATIONS = 6 - 1; - localparam CTRL_IDLE = 4'h0; - localparam CTRL_INIT_WAIT = 4'h1; - localparam CTRL_NEXT_WSTART = 4'h2; - localparam CTRL_NEXT_USTART = 4'h3; - localparam CTRL_NEXT_LOOP0 = 4'h4; - localparam CTRL_NEXT_LOOP = 4'h5; - localparam CTRL_NEXT_WAIT = 4'h6; - localparam CTRL_NEXT_UPDATE = 4'h7; - localparam CTRL_NEXT_WCHECK = 4'h8; - localparam CTRL_NEXT_UCHECK = 4'h9; - localparam CTRL_NEXT_FINALIZE = 4'ha; + localparam CTRL_RESET = 4'h0; + localparam CTRL_IDLE = 4'h1; + localparam CTRL_INIT_WAIT = 4'h2; + localparam CTRL_NEXT_WSTART = 4'h3; + localparam CTRL_NEXT_USTART = 4'h4; + localparam CTRL_NEXT_LOOP0 = 4'h5; + localparam CTRL_NEXT_LOOP = 4'h6; + localparam CTRL_NEXT_WAIT = 4'h7; + localparam CTRL_NEXT_UPDATE = 4'h8; + localparam CTRL_NEXT_WCHECK = 4'h9; + localparam CTRL_NEXT_UCHECK = 4'ha; + localparam CTRL_NEXT_FINALIZE = 4'hb; + localparam CTRL_MKM_WAIT = 4'hc; //---------------------------------------------------------------- @@ -130,6 +143,7 @@ module keywrap_core #(parameter MEM_BITS = 11) wire aes_valid; reg [127 : 0] aes_block; wire [127 : 0] aes_result; + reg [255 : 0] aes_key; reg update_state; @@ -138,6 +152,15 @@ module keywrap_core #(parameter MEM_BITS = 11) reg [63 : 0] core_wr_data; wire [63 : 0] core_rd_data; + reg mkm_init; + reg mkm_read; + reg mkm_write; + reg mkm_key_status; + wire mkm_ready; + wire [255 : 0] mkm_rd_key; + wire [31 : 0] mkm_rd_status; + wire [31 : 0] mkm_wr_status; + //---------------------------------------------------------------- // Instantiations. @@ -166,7 +189,7 @@ module keywrap_core #(parameter MEM_BITS = 11) .init(aes_init), .next(aes_next), - .key(key), + .key(aes_key), .keylen(keylen), .block(aes_block), @@ -177,12 +200,36 @@ module keywrap_core #(parameter MEM_BITS = 11) ); + keywrap_mkmif mkmif( + .clk(clk), + .reset_n(reset_n), + + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), + + .init(mkm_init), + .read(mkm_read), + .write(mkm_write), + .key_status(mkey_mstatus), + .ready(mkm_ready), + + .wr_status(mkm_wr_status), + .rd_status(mkm_rd_status), + .wr_key(key), + .rd_key(mkm_rd_key) + ); + + //---------------------------------------------------------------- // Assignments for ports. //---------------------------------------------------------------- - assign a_result = a_reg; - assign ready = ready_reg; - assign valid = valid_reg; + assign a_result = a_reg; + assign ready = ready_reg; + assign valid = valid_reg; + assign mkey = mkm_rd_key; + assign mstatus = mkm_rd_status; //---------------------------------------------------------------- @@ -190,6 +237,8 @@ module keywrap_core #(parameter MEM_BITS = 11) //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) begin: reg_update + integer i; + if (!reset_n) begin a_reg <= 64'h0; @@ -197,7 +246,7 @@ module keywrap_core #(parameter MEM_BITS = 11) valid_reg <= 1'h0; block_ctr_reg <= {(MEM_BITS - 1){1'h0}}; iteration_ctr_reg <= 3'h0; - keywrap_core_ctrl_reg <= CTRL_IDLE; + keywrap_core_ctrl_reg <= CTRL_RESET; end else @@ -333,6 +382,17 @@ module keywrap_core #(parameter MEM_BITS = 11) end + //---------------------------------------------------------------- + // aes_key_mux + //---------------------------------------------------------------- + always @* + begin + if (mkey_key) + aes_key = mkm_rd_key; + else + aes_key = key; + end + //---------------------------------------------------------------- // keywrap_core_ctrl @@ -347,6 +407,9 @@ module keywrap_core #(parameter MEM_BITS = 11) update_state = 1'h0; aes_init = 1'h0; aes_next = 1'h0; + mkm_init = 1'h0; + mkm_read = 1'h0; + mkm_write = 1'h0; block_ctr_dec = 1'h0; block_ctr_inc = 1'h0; block_ctr_rst = 1'h0; @@ -355,11 +418,22 @@ module keywrap_core #(parameter MEM_BITS = 11) iteration_ctr_dec = 1'h0; iteration_ctr_set = 1'h0; iteration_ctr_rst = 1'h0; + keywrap_core_ctrl_new = CTRL_IDLE; keywrap_core_ctrl_we = 1'h0; case (keywrap_core_ctrl_reg) + CTRL_RESET: + begin + mkm_init = 1'h1; + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_WAIT; + keywrap_core_ctrl_we = 1'h0; + end + + CTRL_IDLE: begin if (init) @@ -386,6 +460,25 @@ module keywrap_core #(parameter MEM_BITS = 11) keywrap_core_ctrl_new = CTRL_NEXT_USTART; keywrap_core_ctrl_we = 1'h1; end + + if (read) + begin + mkm_read = 1'h1; + ready_new = 1'h0; + ready_we = 1'h1; + mkm_read = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_WAIT; + keywrap_core_ctrl_we = 1'h1; + end + + if (write) + begin + mkm_write = 1'h1; + ready_new = 1'h0; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_MKM_WAIT; + keywrap_core_ctrl_we = 1'h1; + end end @@ -517,9 +610,19 @@ module keywrap_core #(parameter MEM_BITS = 11) end - default: + CTRL_MKM_WAIT: begin + if (mkm_ready) + begin + ready_new = 1'h1; + ready_we = 1'h1; + keywrap_core_ctrl_new = CTRL_IDLE; + keywrap_core_ctrl_we = 1'h1; + end + end + default: + begin end endcase // case (keywrap_core_ctrl_reg) end // keywrap_core_ctrl |