diff options
Diffstat (limited to 'src/rtl/keywrap.v')
| -rw-r--r-- | src/rtl/keywrap.v | 146 |
1 files changed, 107 insertions, 39 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v index 2033b23..2e9a7f6 100644 --- a/src/rtl/keywrap.v +++ b/src/rtl/keywrap.v @@ -53,6 +53,11 @@ module keywrap #(parameter ADDR_BITS = 12) input wire clk, input wire reset_n, + output wire mkm_spi_sclk, + output wire mkm_spi_cs_n, + input wire mkm_spi_do, + output wire mkm_spi_di, + input wire cs, input wire we, @@ -65,42 +70,52 @@ module keywrap #(parameter ADDR_BITS = 12) //---------------------------------------------------------------- // Internal constant and parameter definitions. //---------------------------------------------------------------- - localparam ADDR_NAME0 = 8'h00; - localparam ADDR_NAME1 = 8'h01; - localparam ADDR_VERSION = 8'h02; + localparam ADDR_NAME0 = 8'h00; + localparam ADDR_NAME1 = 8'h01; + localparam ADDR_VERSION = 8'h02; - localparam ADDR_CTRL = 8'h08; - localparam CTRL_INIT_BIT = 0; - localparam CTRL_NEXT_BIT = 1; + localparam ADDR_CTRL = 8'h08; + localparam CTRL_INIT_BIT = 0; + localparam CTRL_NEXT_BIT = 1; + localparam CTRL_READ_BIT = 2; + localparam CTRL_WRITE_BIT = 3; localparam ADDR_STATUS = 8'h09; localparam STATUS_READY_BIT = 0; localparam STATUS_VALID_BIT = 1; - localparam ADDR_CONFIG = 8'h0a; - localparam CTRL_ENCDEC_BIT = 0; - localparam CTRL_KEYLEN_BIT = 1; + localparam ADDR_CONFIG = 8'h0a; + localparam CONFIG_ENCDEC_BIT = 0; + localparam CONFIG_KEYLEN_BIT = 1; + localparam CONFIG_MKS_BIT = 2; + + localparam ADDR_RLEN = 8'h0c; + localparam ADDR_A0 = 8'h0e; + localparam ADDR_A1 = 8'h0f; + + localparam ADDR_KEY0 = 8'h10; + localparam ADDR_KEY1 = 8'h11; + localparam ADDR_KEY2 = 8'h12; + localparam ADDR_KEY3 = 8'h13; + localparam ADDR_KEY4 = 8'h14; + localparam ADDR_KEY5 = 8'h15; + localparam ADDR_KEY6 = 8'h16; + localparam ADDR_KEY7 = 8'h17; - localparam ADDR_RLEN = 8'h0c; - localparam ADDR_A0 = 8'h0e; - localparam ADDR_A1 = 8'h0f; + localparam ADDR_MSTATUS = 8'h20; - localparam ADDR_KEY0 = 8'h10; - localparam ADDR_KEY1 = 8'h11; - localparam ADDR_KEY2 = 8'h12; - localparam ADDR_KEY3 = 8'h13; - localparam ADDR_KEY4 = 8'h14; - localparam ADDR_KEY5 = 8'h15; - localparam ADDR_KEY6 = 8'h16; - localparam ADDR_KEY7 = 8'h17; + localparam CORE_NAME0 = 32'h6b657920; // "key " + localparam CORE_NAME1 = 32'h77726170; // "wrap" + localparam CORE_VERSION = 32'h302e3830; // "0.80" - localparam CORE_NAME0 = 32'h6b657920; // "key " - localparam CORE_NAME1 = 32'h77726170; // "wrap" - localparam CORE_VERSION = 32'h302e3830; // "0.80" + localparam MEM_BITS = ADDR_BITS - 1; + localparam RLEN_BITS = ADDR_BITS - 2; + localparam PAD = ADDR_BITS - 8; - localparam MEM_BITS = ADDR_BITS - 1; - localparam RLEN_BITS = ADDR_BITS - 2; - localparam PAD = ADDR_BITS - 8; + + // If set to one, will allow read access to key memory. + // Should be set to zero in all production FPGA bitstreams. + localparam DEBUG_MKM_READ = 1'h1; //---------------------------------------------------------------- @@ -112,6 +127,15 @@ module keywrap #(parameter ADDR_BITS = 12) reg next_reg; reg next_new; + reg read_reg; + reg read_new; + + reg write_reg; + reg write_new; + + reg mkey_mstatus_reg; + reg mkey_mstatus_new; + reg encdec_reg; reg keylen_reg; reg config_we; @@ -128,6 +152,9 @@ module keywrap #(parameter ADDR_BITS = 12) reg [31 : 0] key_reg [0 : 7]; reg key_we; + reg [31 : 0] mstatus_reg; + reg mstatus_we; + reg [31 : 0] api_rd_delay_reg; reg [31 : 0] api_rd_delay_new; @@ -146,6 +173,8 @@ module keywrap #(parameter ADDR_BITS = 12) wire core_ready; wire core_valid; wire [255 : 0] core_key; + wire [255 : 0] core_mkey; + wire [31 : 0] core_mstatus; wire [63 : 0] core_a_init; wire [63 : 0] core_a_result; wire [31 : 0] core_api_rd_data; @@ -166,15 +195,23 @@ module keywrap #(parameter ADDR_BITS = 12) //---------------------------------------------------------------- - // core instantiation. + // keywrap core instantiation. //---------------------------------------------------------------- keywrap_core #(.MEM_BITS(MEM_BITS)) core( .clk(clk), .reset_n(reset_n), + .mkm_spi_sclk(mkm_spi_sclk), + .mkm_spi_cs_n(mkm_spi_cs_n), + .mkm_spi_do(mkm_spi_do), + .mkm_spi_di(mkm_spi_di), + .init(init_reg), .next(next_reg), + .read(read_reg), + .write(write_reg), + .mkey_mstatus(mkey_mstatus_reg), .encdec(encdec_reg), .ready(core_ready), @@ -184,6 +221,9 @@ module keywrap #(parameter ADDR_BITS = 12) .key(core_key), .keylen(keylen_reg), + .status(mstatus_reg), + .mkey(core_mkey), + .mstatus(core_mstatus), .a_init(core_a_init), .a_result(core_a_result), @@ -209,8 +249,12 @@ module keywrap #(parameter ADDR_BITS = 12) init_reg <= 1'h0; next_reg <= 1'h0; + read_reg <= 1'h0; + write_reg <= 1'h0; + mkey_mstatus_reg <= 1'h0; encdec_reg <= 1'h0; keylen_reg <= 1'h0; + mstatus_reg <= 32'h0; rlen_reg <= {RLEN_BITS{1'h0}}; valid_reg <= 1'h0; ready_reg <= 1'h0; @@ -224,12 +268,16 @@ module keywrap #(parameter ADDR_BITS = 12) valid_reg <= core_valid; init_reg <= init_new; next_reg <= next_new; + read_reg <= read_new; + write_reg <= write_new; + mkey_mstatus_reg <= mkey_mstatus_new; api_rd_delay_reg <= api_rd_delay_new; if (config_we) begin - encdec_reg <= write_data[CTRL_ENCDEC_BIT]; - keylen_reg <= write_data[CTRL_KEYLEN_BIT]; + mkey_mstatus_reg <= write_data[CONFIG_MKS_BIT]; + encdec_reg <= write_data[CONFIG_ENCDEC_BIT]; + keylen_reg <= write_data[CONFIG_KEYLEN_BIT]; end if (rlen_we) @@ -241,6 +289,9 @@ module keywrap #(parameter ADDR_BITS = 12) if (a1_we) a1_reg <= write_data; + if (mstatus_we) + mstatus_reg <= write_data; + if (key_we) key_reg[address[2 : 0]] <= write_data; end @@ -256,21 +307,25 @@ module keywrap #(parameter ADDR_BITS = 12) begin : api init_new = 1'h0; next_new = 1'h0; + read_new = 1'h0; + write_new = 1'h0; config_we = 1'h0; rlen_we = 1'h0; key_we = 1'h0; core_api_we = 1'h0; a0_we = 1'h0; a1_we = 1'h0; + mstatus_we = 1'h0; tmp_read_data = 32'h0; tmp_error = 1'h0; api_rd_delay_new = 32'h0; // api_mux - if (address[(ADDR_BITS - 1)]) - tmp_read_data = core_api_rd_data; - else - tmp_read_data = api_rd_delay_reg; + if (core_ready) + if (address[(ADDR_BITS - 1)]) + tmp_read_data = core_api_rd_data; + else + tmp_read_data = api_rd_delay_reg; if (cs) begin @@ -280,8 +335,10 @@ module keywrap #(parameter ADDR_BITS = 12) begin if (address == {{PAD{1'h0}}, ADDR_CTRL}) begin - init_new = write_data[CTRL_INIT_BIT]; - next_new = write_data[CTRL_NEXT_BIT]; + init_new = write_data[CTRL_INIT_BIT]; + next_new = write_data[CTRL_NEXT_BIT]; + read_new = write_data[CTRL_READ_BIT]; + write_new = write_data[CTRL_WRITE_BIT]; end if (address == {{PAD{1'h0}}, ADDR_CONFIG}) @@ -296,6 +353,9 @@ module keywrap #(parameter ADDR_BITS = 12) if (address == {{PAD{1'h0}}, ADDR_A1}) a1_we = 1'h1; + if (address == {{PAD{1'h0}}, ADDR_MSTATUS}) + mstatus_we = 1'h1; + if ((address >= {{PAD{1'h0}}, ADDR_KEY0}) && (address <= {{PAD{1'h0}}, ADDR_KEY7})) key_we = 1'h1; @@ -317,12 +377,10 @@ module keywrap #(parameter ADDR_BITS = 12) api_rd_delay_new = CORE_VERSION; if (address == {{PAD{1'h0}}, ADDR_CTRL}) - api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg}; + api_rd_delay_new = {26'h0, keylen_reg, encdec_reg, write_reg, read_reg, next_reg, init_reg}; if (address == {{PAD{1'h0}}, ADDR_STATUS}) - begin - api_rd_delay_new = {30'h0, valid_reg, ready_reg}; - end + api_rd_delay_new = {30'h0, valid_reg, ready_reg}; if (address == {{PAD{1'h0}}, ADDR_RLEN}) api_rd_delay_new = {{(32 - RLEN_BITS){1'h0}}, rlen_reg}; @@ -332,6 +390,16 @@ module keywrap #(parameter ADDR_BITS = 12) if (address == {{PAD{1'h0}}, ADDR_A1}) api_rd_delay_new = core_a_result[31 : 0]; + + if (address == {{PAD{1'h0}}, ADDR_MSTATUS}) + api_rd_delay_new = core_mstatus; + + // Warning: Should be disabled after mkmif + // integration has been completed. + if (DEBUG_MKM_READ) + if ((address >= {{PAD{1'h0}},ADDR_KEY0}) && (address <= {{PAD{1'h0}}, ADDR_KEY7})) + api_rd_delay_new = core_mkey[(7 - (address - {{PAD{1'h0}}, ADDR_KEY7})) * 32 +: 32]; + end // else: !if(we) end // if (cs) end // block: api |