Adding top level defines for setting size and address bits.

2 files changed, 19 insertions, 2 deletions

diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 885578b..6a28133 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -47,12 +47,28 @@ module keywrap(
                input wire           we,
 
                // Data ports.
-               input wire  [7 : 0]  address,
+               input wire  [(ASPACE - 1) : 0] address,
                input wire  [31 : 0] write_data,
                output wire [31 : 0] read_data,
                output wire          error
               );
 
+  //----------------------------------------------------------------
+  // External parameters
+  //----------------------------------------------------------------
+  // Since $clog2() is not supported by all tools, and constant
+  // functions are not supported by some other tools we need to
+  // do the size to number of bits calculation by hand.
+  // 8192 bytes = 2048 32 bit words. This requires 11 bits.
+  // We need additional space for control and status words. But
+  // since we have filled the address space, we need another MSB
+  // in the address - 12 bits.
+  //
+  // 0x000 - 0x7ff are for control and status.
+  // 0x800 - 0xfff are for data storage
+  parameter ASPACE = 12;
+  localparam MEM_SPACE = (ASPACE / 2);
+
 
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v
index 412bdb2..c53790b 100644
--- a/src/tb/tb_keywrap.v
+++ b/src/tb/tb_keywrap.v
@@ -80,6 +80,7 @@ module tb_keywrap();
   localparam ADDR_R_DATA0     = 8'h80;
   localparam ADDR_R_DATA127   = 8'hff;
 
+  localparam DUT_ASPACE      = 12;
 
   //----------------------------------------------------------------
   // Register and Wire declarations.
@@ -95,7 +96,7 @@ module tb_keywrap();
   reg           tb_reset_n;
   reg           tb_cs;
   reg           tb_we;
-  reg [7  : 0]  tb_address;
+  reg [(DUT_ASPACE - 1) : 0]  tb_address;
   reg [31 : 0]  tb_write_data;
   wire [31 : 0] tb_read_data;
   wire          tb_error;