| Mode | Name | Size | |
|---|---|---|---|
| d--------- | fake_modules | 90 | logplain |
| -rw-r--r-- | tb_csprng.v | 10360 | logplainblame |
| -rw-r--r-- | tb_mixer.v | 9117 | logplainblame |
| -rw-r--r-- | tb_trng.v | 7495 | logplainblame |
 |
index : core/rng/trng | |
| True Random Number Generator core implemented in Verilog | git repositories |
| aboutsummaryrefslogtreecommitdiff |