| Mode | Name | Size | |
|---|---|---|---|
| d--------- | fake_modules | 44 | logplain |
| -rw-r--r-- | tb_csprng.v | 11825 | logplainblame |
| -rw-r--r-- | tb_mixer.v | 11189 | logplainblame |
| -rw-r--r-- | tb_trng.v | 11533 | logplainblame |
 |
index : core/rng/trng | |
| True Random Number Generator core implemented in Verilog | git repositories |
| aboutsummaryrefslogtreecommitdiff |