From d69f5a8b39889e685e89bd938fe899dcacbc003b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 11 Sep 2014 18:25:45 +0200 Subject: Adding initial versions of rtl and tb for the mixer. --- src/tb/tb_mixer.v | 223 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) create mode 100644 src/tb/tb_mixer.v (limited to 'src/tb') diff --git a/src/tb/tb_mixer.v b/src/tb/tb_mixer.v new file mode 100644 index 0000000..c135b61 --- /dev/null +++ b/src/tb/tb_mixer.v @@ -0,0 +1,223 @@ +//====================================================================== +// +// tb_mixer.v +// ----------- +// Testbench for the mixer module in the trng. +// +// +// Author: Joachim Strombergson +// Copyright (c) 2014, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +//------------------------------------------------------------------ +// Simulator directives. +//------------------------------------------------------------------ +`timescale 1ns/100ps + + +//------------------------------------------------------------------ +// Test module. +//------------------------------------------------------------------ +module tb_mixer(); + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter DEBUG = 1; + + parameter CLK_HALF_PERIOD = 1; + parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; + + reg tb_clk; + reg tb_reset_n; + reg tb_enable; + + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + trng_mixer dut( + .clk(tb_clk), + .reset_n(tb_reset_n), + .enable(), + .more_seed(), + .entropy0_enabled(), + .entropy0_syn(), + .entropy0_ack(), + .entropy1_enabled(), + .entropy1_syn(), + .entropy1_ack(), + .entropy2_enabled(), + .entropy2_syn(), + .entropy2_ack(), + .seed_data(), + .seed_syn(), + .seed_ack() + ); + + + //---------------------------------------------------------------- + // clk_gen + // + // Always running clock generator process. + //---------------------------------------------------------------- + always + begin : clk_gen + #CLK_HALF_PERIOD; + tb_clk = !tb_clk; + end // clk_gen + + + //---------------------------------------------------------------- + // sys_monitor() + // + // An always running process that creates a cycle counter and + // conditionally displays information about the DUT. + //---------------------------------------------------------------- + always + begin : sys_monitor + cycle_ctr = cycle_ctr + 1; + + #(CLK_PERIOD); + + if (DEBUG) + begin + dump_dut_state(); + end + end + + + //---------------------------------------------------------------- + // dump_dut_state() + // + // Dump the state of the dump when needed. + //---------------------------------------------------------------- + task dump_dut_state(); + begin + $display("cycle: 0x%016x", cycle_ctr); + $display("State of DUT"); + $display("------------"); + $display(""); + end + endtask // dump_dut_state + + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggle reset to put the DUT into a well known state. + //---------------------------------------------------------------- + task reset_dut(); + begin + $display("*** Toggle reset."); + tb_reset_n = 0; + + #(2 * CLK_PERIOD); + tb_reset_n = 1; + $display(""); + end + endtask // reset_dut + + + //---------------------------------------------------------------- + // display_test_results() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_results(); + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully", tc_ctr); + end + else + begin + $display("*** %02d tests completed - %02d test cases did not complete successfully.", + tc_ctr, error_ctr); + end + end + endtask // display_test_results + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim(); + begin + cycle_ctr = 0; + error_ctr = 0; + tc_ctr = 0; + + tb_clk = 0; + tb_reset_n = 1; + tb_enable = 0; + end + endtask // init_sim + + + //---------------------------------------------------------------- + // mixer_test + // + // The main test functionality. + //---------------------------------------------------------------- + initial + begin : mixer_test + + $display(" -= Testbench for mixer started =-"); + $display(" ================================"); + $display(""); + + init_sim(); + dump_dut_state(); + reset_dut(); + dump_dut_state(); + + display_test_results(); + + $display(""); + $display("*** Mixer simulation done. ***"); + $finish; + end // mixer_test +endmodule // tb_mixer + +//====================================================================== +// EOF tb_mixer.v +//====================================================================== -- cgit v1.2.3