From 56e604d14a4c4121a0f188534b1811422c165eb8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Tue, 27 Mar 2018 13:26:44 +0200
Subject: Fixed build and lint warnings. Cleaned up constant declarations.
 Changed asynch reset that collidsed with sync reset in other modules.

---
 src/tb/tb_trng.v | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

(limited to 'src/tb/tb_trng.v')

diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v
index 38d2559..27097bc 100644
--- a/src/tb/tb_trng.v
+++ b/src/tb/tb_trng.v
@@ -36,11 +36,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
 
 //------------------------------------------------------------------
 // Test module.
@@ -182,7 +177,7 @@ module tb_trng();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -247,7 +242,7 @@ module tb_trng();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -264,7 +259,7 @@ module tb_trng();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -285,7 +280,7 @@ module tb_trng();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr          = 0;
       error_ctr          = 0;
@@ -310,7 +305,7 @@ module tb_trng();
   // A simple first testcase that tries to make the DUT generate
   // a number of random values.
   //----------------------------------------------------------------
-  task tc1_gen_rnd();
+  task tc1_gen_rnd;
     reg [31 : 0] i;
 
     begin
-- 
cgit v1.2.3