From e786303f0d2778f7c26cbb443831823c82429205 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 16 Oct 2018 11:13:50 +0200 Subject: (1) Fixed width definitions and cleaned up constants as part of checking that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint. --- src/tb/tb_csprng.v | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'src/tb/tb_csprng.v') diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v index 3b4d787..1f4d82e 100644 --- a/src/tb/tb_csprng.v +++ b/src/tb/tb_csprng.v @@ -37,12 +37,6 @@ // //====================================================================== -//------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/100ps - - //------------------------------------------------------------------ // Test module. //------------------------------------------------------------------ @@ -178,7 +172,7 @@ module tb_csprng(); // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); @@ -272,7 +266,7 @@ module tb_csprng(); // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -289,7 +283,7 @@ module tb_csprng(); // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_results(); + task display_test_results; begin if (error_ctr == 0) begin @@ -310,7 +304,7 @@ module tb_csprng(); // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 0; error_ctr = 0; @@ -396,7 +390,7 @@ module tb_csprng(); // enable is set. We also starts pulling random data from the // csprng to see that it actually emits data as expected. //---------------------------------------------------------------- - task tc1_init_csprng(); + task tc1_init_csprng; begin tc_ctr = tc_ctr + 1; @@ -419,7 +413,7 @@ module tb_csprng(); // TC2: Test that the CSPRNG is reseeded as expected. // We set the max block size to a small value and pull data. //---------------------------------------------------------------- - task tc2_reseed_csprng(); + task tc2_reseed_csprng; begin tc_ctr = tc_ctr + 1; -- cgit v1.2.3