From d5974ed0d389f8953b23d98bb69b1576adad27b8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Fri, 22 May 2015 10:34:50 +0200
Subject: (1) Added a cipher block statistics counter. (2) Cleaned up the
csprng code and connected discard for fast restart of trng. (3) Added
addresses for allowing API to write a known seed to allow test mode. (3)
Fixed a number of minor issues during linting. (4) Fixed the csprng testbench
to actually generate data as well as displaying the block stat counter.
---
src/tb/fake_modules/avalanche_entropy.v | 4 ++--
src/tb/fake_modules/rosc_entropy.v | 6 ++----
2 files changed, 4 insertions(+), 6 deletions(-)
(limited to 'src/tb/fake_modules')
diff --git a/src/tb/fake_modules/avalanche_entropy.v b/src/tb/fake_modules/avalanche_entropy.v
index 857926c..2caf743 100644
--- a/src/tb/fake_modules/avalanche_entropy.v
+++ b/src/tb/fake_modules/avalanche_entropy.v
@@ -80,9 +80,9 @@ module avalanche_entropy(
.clk(clk),
.reset_n(reset_n),
- .enable(1),
+ .enable(1'b1),
- .raw_entropy(noise),
+ .raw_entropy(),
.stats(),
.enabled(entropy_enabled),
diff --git a/src/tb/fake_modules/rosc_entropy.v b/src/tb/fake_modules/rosc_entropy.v
index b66bd90..add8b7a 100644
--- a/src/tb/fake_modules/rosc_entropy.v
+++ b/src/tb/fake_modules/rosc_entropy.v
@@ -41,8 +41,6 @@ module rosc_entropy(
input wire clk,
input wire reset_n,
- input wire noise,
-
input wire cs,
input wire we,
input wire [7 : 0] address,
@@ -80,9 +78,9 @@ module rosc_entropy(
.clk(clk),
.reset_n(reset_n),
- .enable(1),
+ .enable(1'b1),
- .raw_entropy(noise),
+ .raw_entropy(),
.stats(),
.enabled(entropy_enabled),
--
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