From e786303f0d2778f7c26cbb443831823c82429205 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 16 Oct 2018 11:13:50 +0200 Subject: (1) Fixed width definitions and cleaned up constants as part of checking that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint. --- src/rtl/trng.v | 6 ++-- src/rtl/trng_csprng.v | 28 ++++++++-------- src/rtl/trng_csprng_fifo.v | 23 ++++++------- src/rtl/trng_mixer.v | 80 +++++++++++++++++++++++----------------------- 4 files changed, 69 insertions(+), 68 deletions(-) (limited to 'src/rtl') diff --git a/src/rtl/trng.v b/src/rtl/trng.v index c10e846..107a0b1 100644 --- a/src/rtl/trng.v +++ b/src/rtl/trng.v @@ -341,12 +341,12 @@ module trng( begin if (!reset_n) begin - discard_reg <= 0; - test_mode_reg <= 0; + discard_reg <= 1'h0; + test_mode_reg <= 1'h0; debug_mux_reg <= DEBUG_CSPRNG; debug_delay_reg <= DEFAULT_DEBUG_DELAY; debug_delay_ctr_reg <= 32'h00000000; - debug_out_reg <= 8'h00; + debug_out_reg <= 8'h0; end else begin diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v index c682f27..872cb1e 100644 --- a/src/rtl/trng_csprng.v +++ b/src/rtl/trng_csprng.v @@ -194,8 +194,6 @@ module trng_csprng( reg [3 : 0] csprng_ctrl_new; reg csprng_ctrl_we; - reg [31 : 0] tmp_read_data; - //---------------------------------------------------------------- // Wires. @@ -218,6 +216,8 @@ module trng_csprng( wire muxed_rnd_ack; + reg [31 : 0] tmp_read_data; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -281,18 +281,18 @@ module trng_csprng( begin if (!reset_n) begin - cipher_key_reg <= {8{32'h00000000}}; - cipher_iv_reg <= {2{32'h00000000}}; - cipher_ctr_reg <= {2{32'h00000000}}; - cipher_block_reg <= {16{32'h00000000}}; - block_ctr_reg <= {2{32'h00000000}}; - block_stat_ctr_reg <= {2{32'h00000000}}; - reseed_stat_ctr_reg <= 32'h00000000; - more_seed_reg <= 0; - seed_ack_reg <= 0; - ready_reg <= 0; - enable_reg <= 1; - seed_reg <= 0; + cipher_key_reg <= 256'h0; + cipher_iv_reg <= 64'h0; + cipher_ctr_reg <= 64'h0; + cipher_block_reg <= 512'h0; + block_ctr_reg <= 64'h0; + block_stat_ctr_reg <= 64'h0; + reseed_stat_ctr_reg <= 32'h0; + more_seed_reg <= 1'h0; + seed_ack_reg <= 1'h0; + ready_reg <= 1'h0; + enable_reg <= 1'h1; + seed_reg <= 1'h0; num_rounds_reg <= DEFAULT_NUM_ROUNDS; num_blocks_low_reg <= DEFAULT_NUM_BLOCKS[31 : 0]; num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32]; diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v index db0a1be..5fbce89 100644 --- a/src/rtl/trng_csprng_fifo.v +++ b/src/rtl/trng_csprng_fifo.v @@ -142,20 +142,21 @@ module trng_csprng_fifo( // Register update. All registers have asynchronous reset. //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) - begin + begin : reg_update + integer i; + if (!reset_n) begin - fifo_mem[00] <= {16{32'h00000000}}; - fifo_mem[01] <= {16{32'h00000000}}; - fifo_mem[02] <= {16{32'h00000000}}; - fifo_mem[03] <= {16{32'h00000000}}; + for (i = 0 ; i < FIFO_MAX ; i = i + 1) + fifo_mem[i] <= 512'h0; + mux_data_ptr_reg <= 4'h0; - rd_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}}; - wr_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}}; - fifo_ctr_reg <= {FIFO_ADDR_BITS{1'b0}}; - rnd_data_reg <= 32'h00000000; - rnd_syn_reg <= 0; - more_data_reg <= 0; + rd_ptr_reg <= {(FIFO_ADDR_BITS){1'h0}}; + wr_ptr_reg <= {(FIFO_ADDR_BITS){1'h0}}; + fifo_ctr_reg <= {FIFO_ADDR_BITS{1'h0}}; + rnd_data_reg <= 32'h0; + rnd_syn_reg <= 1'h0; + more_data_reg <= 1'h0; wr_ctrl_reg <= WR_IDLE; rd_ctrl_reg <= RD_IDLE; end diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v index 06e3323..1a70e27 100644 --- a/src/rtl/trng_mixer.v +++ b/src/rtl/trng_mixer.v @@ -225,8 +225,6 @@ module trng_mixer( reg restart_reg; reg restart_new; - reg [31 : 0] tmp_read_data; - //---------------------------------------------------------------- // Wires. @@ -254,6 +252,8 @@ module trng_mixer( reg tmp_error; + reg [31 : 0] tmp_read_data; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -319,45 +319,45 @@ module trng_mixer( begin if (!reset_n) begin - block00_reg <= 32'h00000000; - block01_reg <= 32'h00000000; - block02_reg <= 32'h00000000; - block03_reg <= 32'h00000000; - block04_reg <= 32'h00000000; - block05_reg <= 32'h00000000; - block06_reg <= 32'h00000000; - block07_reg <= 32'h00000000; - block08_reg <= 32'h00000000; - block09_reg <= 32'h00000000; - block10_reg <= 32'h00000000; - block11_reg <= 32'h00000000; - block12_reg <= 32'h00000000; - block13_reg <= 32'h00000000; - block14_reg <= 32'h00000000; - block15_reg <= 32'h00000000; - block16_reg <= 32'h00000000; - block17_reg <= 32'h00000000; - block18_reg <= 32'h00000000; - block19_reg <= 32'h00000000; - block20_reg <= 32'h00000000; - block21_reg <= 32'h00000000; - block22_reg <= 32'h00000000; - block23_reg <= 32'h00000000; - block24_reg <= 32'h00000000; - block25_reg <= 32'h00000000; - block26_reg <= 32'h00000000; - block27_reg <= 32'h00000000; - block28_reg <= 32'h00000000; - block29_reg <= 32'h00000000; - block30_reg <= 32'h00000000; - block31_reg <= 32'h00000000; - init_done_reg <= 0; - word_ctr_reg <= 5'h00; - seed_syn_reg <= 0; - enable_reg <= 1; - restart_reg <= 0; + block00_reg <= 32'h0; + block01_reg <= 32'h0; + block02_reg <= 32'h0; + block03_reg <= 32'h0; + block04_reg <= 32'h0; + block05_reg <= 32'h0; + block06_reg <= 32'h0; + block07_reg <= 32'h0; + block08_reg <= 32'h0; + block09_reg <= 32'h0; + block10_reg <= 32'h0; + block11_reg <= 32'h0; + block12_reg <= 32'h0; + block13_reg <= 32'h0; + block14_reg <= 32'h0; + block15_reg <= 32'h0; + block16_reg <= 32'h0; + block17_reg <= 32'h0; + block18_reg <= 32'h0; + block19_reg <= 32'h0; + block20_reg <= 32'h0; + block21_reg <= 32'h0; + block22_reg <= 32'h0; + block23_reg <= 32'h0; + block24_reg <= 32'h0; + block25_reg <= 32'h0; + block26_reg <= 32'h0; + block27_reg <= 32'h0; + block28_reg <= 32'h0; + block29_reg <= 32'h0; + block30_reg <= 32'h0; + block31_reg <= 32'h0; + init_done_reg <= 1'h0; + word_ctr_reg <= 5'h0; + seed_syn_reg <= 1'h0; + enable_reg <= 1'h1; + restart_reg <= 1'h0; entropy_timeout_reg <= DEFAULT_ENTROPY_TIMEOUT; - entropy_timeout_ctr_reg <= 24'h000000; + entropy_timeout_ctr_reg <= 24'h0; entropy_collect_ctrl_reg <= CTRL_IDLE; mixer_ctrl_reg <= CTRL_IDLE; end -- cgit v1.2.3