From e786303f0d2778f7c26cbb443831823c82429205 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Tue, 16 Oct 2018 11:13:50 +0200 Subject: (1) Fixed width definitions and cleaned up constants as part of checking that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint. --- src/rtl/trng_csprng.v | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'src/rtl/trng_csprng.v') diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v index c682f27..872cb1e 100644 --- a/src/rtl/trng_csprng.v +++ b/src/rtl/trng_csprng.v @@ -194,8 +194,6 @@ module trng_csprng( reg [3 : 0] csprng_ctrl_new; reg csprng_ctrl_we; - reg [31 : 0] tmp_read_data; - //---------------------------------------------------------------- // Wires. @@ -218,6 +216,8 @@ module trng_csprng( wire muxed_rnd_ack; + reg [31 : 0] tmp_read_data; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -281,18 +281,18 @@ module trng_csprng( begin if (!reset_n) begin - cipher_key_reg <= {8{32'h00000000}}; - cipher_iv_reg <= {2{32'h00000000}}; - cipher_ctr_reg <= {2{32'h00000000}}; - cipher_block_reg <= {16{32'h00000000}}; - block_ctr_reg <= {2{32'h00000000}}; - block_stat_ctr_reg <= {2{32'h00000000}}; - reseed_stat_ctr_reg <= 32'h00000000; - more_seed_reg <= 0; - seed_ack_reg <= 0; - ready_reg <= 0; - enable_reg <= 1; - seed_reg <= 0; + cipher_key_reg <= 256'h0; + cipher_iv_reg <= 64'h0; + cipher_ctr_reg <= 64'h0; + cipher_block_reg <= 512'h0; + block_ctr_reg <= 64'h0; + block_stat_ctr_reg <= 64'h0; + reseed_stat_ctr_reg <= 32'h0; + more_seed_reg <= 1'h0; + seed_ack_reg <= 1'h0; + ready_reg <= 1'h0; + enable_reg <= 1'h1; + seed_reg <= 1'h0; num_rounds_reg <= DEFAULT_NUM_ROUNDS; num_blocks_low_reg <= DEFAULT_NUM_BLOCKS[31 : 0]; num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32]; -- cgit v1.2.3